Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10043772-B2
Application number	US-201715489117-A
Country	US
Kind code	B2
Filing date	Apr 17, 2017
Priority date	Jun 23, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the semiconductor chip; and
connection terminals disposed on the second interconnection member,
wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads of the semiconductor chip, and
the connection pads and the connection terminals are electrically connected to each other by an electrical pathway traversing the redistribution layer of the first interconnection member.

2. The fan-out semiconductor package of claim 1 , wherein the electrical pathway traverses the connection terminal, the redistribution layer of the second interconnection member, the redistribution layer of the first interconnection member, the redistribution layer of the second interconnection member, and the connection terminal in sequence.

3. The fan-out semiconductor package of claim 1 , wherein the first interconnection member has a first side and a second side opposing the first side, each of the first and the second sides having a redistribution layer, and
the electrical pathway traverses the redistribution layer disposed on the first side of the first interconnection member, a first via penetrating through the first interconnection member, the redistribution layer disposed on the second side of the first interconnection member, a second via penetrating through the first interconnection member, and the redistribution layer disposed on the first side of the first interconnection member in sequence.

4. The fan-out semiconductor package of claim 1 , wherein the redistribution layer of the first interconnection member includes a via pad, and
a horizontal cross-sectional area of the via pad of the redistribution layer of the first interconnection member is equal to or greater than that of the connection pad of the semiconductor chip.

5. The fan-out semiconductor package of claim 1 , wherein the redistribution layers of the first interconnection member and the second interconnection member respectively include via pads, and
a horizontal cross-sectional area of the via pad of the redistribution layer of the first interconnection member is equal to or greater than that of the via pad of the redistribution layer of the second interconnection member.

6. The fan-out semiconductor package of claim 1 , wherein the redistribution layer of the second interconnection member includes a via pad, and
a horizontal cross-sectional area of the connection pad of the semiconductor chip is equal to or greater than that of the via pad of the redistribution layer of the second interconnection member.

7. The fan-out semiconductor package of claim 1 , wherein the first interconnection member includes a first insulating layer, a first redistribution layer in contact with the second interconnection member and embedded in a first surface of the first insulating layer, and a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer.

8. The fan-out semiconductor package of claim 7 , wherein the first interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer.

9. The fan-out semiconductor package of claim 7 , wherein a distance between the redistribution layer of the second interconnection member and the first redistribution layer is greater than that between the redistribution layer of the second interconnection member and the connection pad.

10. The fan-out semiconductor package of claim 7 , wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member.

11. The fan-out semiconductor package of claim 7 , wherein a lower surface of the first redistribution layer is disposed on a level above a lower surface of the connection pad.

12. The fan-out semiconductor package of claim 8 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

13. The fan-out semiconductor package of claim 1 , wherein the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.

14. The fan-out semiconductor package of claim 13 , wherein the first interconnection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer.

15. The fan-out semiconductor package of claim 13 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

16. The fan-out semiconductor package of claim 13 , wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member.

17. The fan-out semiconductor package of claim 13 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

18. The fan-out semiconductor package of claim 13 , wherein a lower surface of the third redistribution layer is disposed on a level below a lower surface of the connection pad.

19. The fan-out semiconductor package of claim 4 , wherein a ratio of the horizontal cross-sectional area of the via pad of the redistribution layer of the first interconnection member to that of the connection pad of the semiconductor chip is greater than 1 and less than or equal to 2.

20. The fan-out semiconductor package of claim 5 , wherein a ratio of the horizontal cross-sectional area of the via pad of the redistribution layer of the first interconnection member to that of the redistribution layer of the second interconnection member is greater than 1 and less than or equal to 2.

21. The fan-out semiconductor package of claim 3 , wherein the redistribution layers disposed on the first and second sides of the first interconnection member each include a via pad, and
a horizontal cross-sectional area of the via pad of the redistribution layer disposed on the first side of the first interconnection member is equal to or greater than that of the redistribution layer disposed on the second side of the first interconnection member.

Assignees

• Samsung Electro Mech

Inventors

• Lee Sang Kyu
• Kim Jin Gu

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title