Fan-out semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9984979-B2
Application number	US-201615297831-A
Country	US
Kind code	B2
Filing date	Oct 19, 2016
Priority date	May 11, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

First claim

What is claimed is:

1. A fan-out semiconductor package, comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads,
wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the first to third redistribution layers of the first connection member are electrically connected to the connection pads.

2. The fan-out semiconductor package of claim 1 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

3. The fan-out semiconductor package of claim 1 , wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second connection member.

4. The fan-out semiconductor package of claim 3 , wherein the third redistribution layer is interposed between the first insulating layer and the second connection member.

5. The fan-out semiconductor package of claim 1 , wherein the third redistribution layer is disposed on a level that is substantially the same as that of the connection pad.

6. The fan-out semiconductor package of claim 1 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

7. The fan-out semiconductor package of claim 1 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the fourth redistribution layer is electrically connected to the connection pads.

8. The fan-out semiconductor package of claim 7 , wherein the semiconductor chip has signal connection pads,
the signal connection pads are electrically connected to signal connection terminals disposed in a fan-out region on the first connection member through an electrical path passing through signal patterns of the redistribution layer of the second connection member, signal patterns of the first redistribution layer of the first connection member, and signal patterns of the fourth redistribution layer of the first connection member, and
the second and third redistribution layers of the first connection member have ground patterns.

9. The fan-out semiconductor package of claim 1 , wherein the semiconductor chip has signal connection pads,
the signal connection pads are electrically connected to signal connection terminals disposed in a fan-out region on the first connection member through an electrical path passing through signal patterns of the redistribution layer of the second connection member and signal patterns of the first redistribution layer of the first connection member, and
the second and third redistribution layers of the first connection member have ground patterns.

10. The fan-out semiconductor package of claim 1 , wherein the semiconductor chip has signal connection pads,
the signal connection pads are electrically connected to signal connection terminals disposed in a fan-out region on the second connection member through an electrical path passing through signal patterns of the redistribution layer of the second connection member and signal patterns of the first redistribution layer of the first connection member, and
the second and third redistribution layers of the first connection member have ground patterns.

11. The fan-out semiconductor package of claim 1 , wherein the second redistribution layer has wire bonding pads exposed externally.

12. The fan-out semiconductor package of claim 1 , wherein the first connection member further includes a first via penetrating through the first insulating layer and connecting the first and second redistribution layers to each other and a second via penetrating through the second insulating layer and connecting the first and third redistribution layers to each other, and
the first via has a diameter greater than that of the second via.

13. The fan-out semiconductor package of claim 1 , wherein the first insulating layer has a modulus of elasticity greater than that of the second insulating layer.

14. The fan-out semiconductor package of claim 1 , wherein the first connection member further includes a metal layer disposed on a wall of the through-hole.

15. The fan-out semiconductor package of claim 1 , further comprising a passive electronic component disposed in the through-hole.

16. The fan-out semiconductor package of claim 1 , wherein the encapsulant includes a core material, an inorganic filler, and an insulating resin.

17. The fan-out semiconductor package of claim 1 , further comprising:
a passivation layer disposed on the second connection member and having openings exposing at least portions of the redistribution layer of the second connection member; and
connection terminals disposed in the openings,
wherein at least one of the connection terminals is disposed in a fan-out region.

18. The fan-out semiconductor package of claim 1 , further comprising a backside redistribution layer disposed on the encapsulant and electrically connected to the first connection member through a backside via penetrating through the encapsulant.

19. The fan-out semiconductor package of claim 18 , further comprising a resin layer disposed on the encapsulant and having openings exposing at least portions of the backside redistribution layer.

20. The fan-out semiconductor package of claim 1 , further comprising a memory package stacked on the encapsulant and electrically connected to the first connection member,
wherein the semiconductor chip includes an application processor chip, and
the memory package includes a memory chip.

21. The fan-out semiconductor package of claim 1 , wherein the encapsulant fills a portion of a space between the semiconductor chip and the second connection member.

22. A fan-out semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
one or more connection units disposed adjacently to the semiconductor chip; and
a connection member disposed on the connection units and the semiconductor chip,
wherein each of the connection units includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer,
the connection member includes an insulating laye

Assignees

• Samsung Electro Mech

Inventors

• Park Dae Hyun
• Kim Han
• Hur Kang Heon
• Ko Young Gwan
• Shim Jung Ho

Classifications

• H05K1/0271

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H05K1/185

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K2201/10674

  Flip chip · CPC title

• H10P72/7442

  Separation by peeling · CPC title

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title