Semiconductor devices

Patent metadata

Field	Value
Publication number	US-10700203-B2
Application number	US-201816213186-A
Country	US
Kind code	B2
Filing date	Dec 7, 2018
Priority date	Jun 20, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of active fins on a substrate;
a gate electrode on the plurality of active fins; and
a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode, the source/drain region comprising lower epitaxial layers and an upper epitaxial layer,
wherein the lower epitaxial layers are on the plurality of the active fins and comprise germanium (Ge) having a first concentration,
wherein an upper epitaxial layer is on the lower epitaxial layers and comprises germanium (Ge) having a second concentration that is higher than the first concentration, and
wherein the lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.

2. The semiconductor device of claim 1 ,
wherein the upper epitaxial layer comprises inclined side surfaces with respect to an upper surface of the substrate,
wherein an upper portion of the upper epitaxial layer overlaps the lower epitaxial layers that are connected to each other.

3. The semiconductor device of claim 2 , wherein the upper epitaxial layer has an upper surface which is flat and is between the inclined side surfaces.

4. The semiconductor device of claim 2 , wherein the upper epitaxial layer has an upper surface which is concave and is between the inclined side surfaces.

5. The semiconductor device of claim 2 ,
wherein the upper epitaxial layer has a groove between the inclined side surfaces, and
wherein the upper epitaxial layer has protruding portions which are pointed.

6. The semiconductor device of claim 1 ,
wherein the source/drain region comprises silicon and germanium,
wherein the first concentration of germanium is in a range of 45 atomic percentage (at %) to 60 at %, and
wherein the second concentration of germanium is in a range of 60 at % to 90 at %.

7. The semiconductor device of claim 1 , further comprising:
a contact plug on the source/drain region,
wherein the contact plug is in contact with the upper epitaxial layer.

8. The semiconductor device of claim 7 , wherein the contact plug comprises a silicide layer that physically contacts the source/drain region.

9. The semiconductor device of claim 1 ,
wherein the plurality of active fins have a recessed area on the first side and the second side of the gate electrode, and
wherein the source/drain region is in the recessed area.

10. The semiconductor device of claim 1 , wherein the upper epitaxial layer comprises a dopant having a third concentration that is higher than a fourth concentration of the dopant in the lower epitaxial layers.

11. The semiconductor device of claim 1 , further comprising:
an air gap between the source/drain regions,
wherein the air gap is between the lower epitaxial layers and an element isolation layer that is on the substrate.

12. The semiconductor device of claim 1 ,
wherein the source/drain region further comprises a capping layer on the upper epitaxial layer, and
wherein the capping layer comprises silicon (Si).

13. A semiconductor device, comprising:
a plurality of active fins on a substrate;
a gate electrode on the plurality of active fins; and
a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode, the source/drain region comprising first epitaxial layers, second epitaxial layers, third epitaxial layers, and a fourth epitaxial layer,
wherein the first epitaxial layers are on ones of the plurality of active fins, and comprise germanium (Ge) having a first concentration,
wherein the second epitaxial layers are on the first epitaxial layers, and comprise germanium (Ge) having a second concentration that is higher than the first concentration,
wherein the third epitaxial layers are on the second epitaxial layers, and comprise germanium (Ge) having a third concentration that is higher than the second concentration,
wherein the fourth epitaxial layer comprises germanium (Ge) having a fourth concentration that is higher than the third concentration,
wherein the fourth epitaxial layer is on the third epitaxial layers, and
wherein the third epitaxial layers have convex upper surfaces, and are connected to each other between the ones of the plurality of active fins.

14. The semiconductor device of claim 13 ,
wherein the fourth epitaxial layer comprises inclined side surfaces with respect to a first upper surface of the substrate, and
wherein the fourth epitaxial layer further comprises a second upper surface which is flat or concave between the inclined side surfaces.

15. The semiconductor device of claim 13 ,
wherein the fourth epitaxial layer comprises inclined side surfaces with respect to a first upper surface of the substrate, and
wherein the fourth epitaxial layer further comprises a groove between the inclined side surfaces.

16. The semiconductor device of claim 13 ,
wherein the source/drain region comprises silicon and germanium,
wherein the first concentration of germanium is in a range of 5 atomic percentage (at %) to 25 at %,
wherein the second concentration of germanium is in a range of 25 at % to 45 at %,
wherein the third concentration of germanium is in a range of 45 at % to 60 at %, and
wherein the fourth concentration of germanium is in a range of 60 at % to 90 at %.

17. The semiconductor device of claim 13 , further comprising:
a contact plug on the source/drain region, and in contact with the fourth epitaxial layer.

18. The semiconductor device of claim 13 , wherein the first epitaxial layers, the second epitaxial layers, the third epitaxial layers, and the fourth epitaxial layer comprise boron (B) having different concentrations.

19. The semiconductor device of claim 13 ,
wherein the source/drain region further comprises a capping layer on the fourth epitaxial layer, and
wherein the capping layer is formed of silicon (Si).

20. A semiconductor device, comprising:
a plurality of active fins on a substrate;
a gate electrode on the plurality of active fins;
a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode; and
a contact plug on the source/drain region,
wherein the source/drain region comprises first epitaxial layers, second epitaxial layers, third epitaxial layers, and a fourth epitaxial layer,
wherein the first epitaxial layers are on ones of the plurality of active fins, and comprise germanium (Ge) having a first concentration,
wherein the second epitaxial layers are on the first epitaxial layers, and comprise germanium (Ge) having a second concentration that is higher than the first concentration,
wherein the third epitaxial layers are on the second epitaxial layers, and comprise germanium (Ge) having a third concentration that is higher than the second concentration,
wherein the fourth epitaxial layer comprises germanium (Ge) having a fourth concentration that is higher than the third concentration,
wherein the fourth epitaxial layer is on the third epitaxial layers,
wherein the third epitaxial layers have convex upper surfaces, and are connected to each other between the ones of the plurality of active fins, and
wherein the contact plug is in contact with the fourth epitaxial layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong Woo
• Kim Do Hee
• Kim Hyo Jin
• Moon Kang Hun
• Lee Si Hyung

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title