Semiconductor device, static random access memory cell and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-9768178-B2
Application number	US-201514938311-A
Country	US
Kind code	B2
Filing date	Nov 11, 2015
Priority date	Nov 11, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first semiconductor fin disposed on the substrate;
a second semiconductor fin disposed on the substrate and adjacent to the first semiconductor fin;
an n-type epitaxy structure disposed on the first semiconductor fin;
a p-type epitaxy structure disposed on the second semiconductor fin and separated from the n-type epitaxy structure; and
a plurality of first dielectric fin sidewall structures disposed on opposite sides of the n-type epitaxy structure, wherein the n-type epitaxy structure comprises:
a top portion having a first width; and
a body portion disposed between the top portion and the first semiconductor fin and having a second width shorter than the first width, wherein the first dielectric fin sidewall structures are disposed on opposite sides of the body portion of the n-type epitaxy structure, and the top portion of the n-type epitaxy structure is disposed on the first dielectric fin sidewall structures.

2. The semiconductor device of claim 1 , wherein the first semiconductor fin has a third width substantially the same as the second width of the body portion of the n-type epitaxy structure.

3. The semiconductor device of claim 1 , wherein the top portion of the n-type epitaxy structure has at least one substantially non-facet surface.

4. The semiconductor device of claim 1 , further comprising a plurality of second dielectric fin sidewall structures disposed on opposite sides of the p-type epitaxy structure.

5. The semiconductor device of claim 1 , further comprising at least one isolation structure adjacent to the first semiconductor fin.

6. The semiconductor device of claim 5 , wherein the isolation structure is present between the first semiconductor fin and the second semiconductor fin.

7. The semiconductor device of claim 1 , further comprising a gate stack covering the first semiconductor fin.

8. The semiconductor device of claim 7 , wherein the gate stack further covers the second semiconductor fin.

9. The semiconductor device of claim 1 , wherein the substrate has at least one p-well region and at least one n-well region, wherein the first semiconductor fin is present on the p-well region, and the second semiconductor fin is present on the n-well region.

10. A method for manufacturing a semiconductor device, the method comprising:
forming a first semiconductor fin and a second semiconductor fin on a substrate, wherein the first semiconductor fin is adjacent to the second semiconductor fin;
forming a plurality of dielectric fin sidewall structures at least on opposite sides of the first semiconductor fin;
recessing the first semiconductor fin;
forming a first epitaxy structure on the recessed first semiconductor fin;
tuning heights of the dielectric fin sidewall structures;
recessing the second semiconductor fin; and
forming a second epitaxy structure on the recessed second semiconductor fin, wherein the first and second epitaxy structures are of different types.

11. The method of claim 10 , wherein the dielectric fin sidewall structures are formed on the opposite sides of the first semiconductor fin and the opposite sides of the second semiconductor fin.

12. The method of claim 10 , wherein the heights of the dielectric fin sidewall structures are tuned by etching.

13. The method of claim 10 , wherein one of the first and second epitaxy structures is of n type, and another of the first and second epitaxy structures is of p type.

14. The method of claim 10 , further comprising:
forming a gate stack on at least one of the first semiconductor fin and the second semiconductor fin.

15. The method of claim 10 , further comprising forming at least one isolation structure adjacent to the first semiconductor fin.

16. The method of claim 10 , further comprising forming a gate stack to cover the first semiconductor fin.

17. A semiconductor device comprising:
a substrate;
a first semiconductor fin disposed on the substrate;
a second semiconductor fin disposed on the substrate and adjacent to the first semiconductor fin;
an n-type epitaxy structure disposed on the first semiconductor fin;
a p-type epitaxy structure disposed on the second semiconductor fin and separated from the n-type epitaxy structure; and
a plurality of first dielectric fin sidewall structures disposed on opposite sides of the p-type epitaxy structure, wherein the p-type epitaxy structure comprises:
a top portion having a first width; and
a body portion disposed between the top portion and the second semiconductor fin and having a second width shorter than the first width, wherein the first dielectric fin sidewall structures are disposed on opposite sides of the body portion of the p-type epitaxy structure, and the top portion of the p-type epitaxy structure is disposed on the first dielectric fin sidewall structures.

18. The semiconductor device of claim 17 , wherein the second semiconductor fin has a third width substantially the same as the second width of the body portion of the p-type epitaxy structure.

19. The semiconductor device of claim 17 , wherein the top portion of the p-type epitaxy structure has at least one substantially facet surface.

20. The semiconductor device of claim 17 , further comprising a plurality of second dielectric fin sidewall structures disposed on opposite sides of the n-type epitaxy structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yi-Jing
• Kwok Tsz-Mei
• Yu Ming-Hua
• Li Kun-Mu

Classifications

• H01L27/1104 Primary

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic