Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations

Patent metadata

Field	Value
Publication number	US-9761719-B2
Application number	US-201514741454-A
Country	US
Kind code	B2
Filing date	Jun 17, 2015
Priority date	Jul 22, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a device isolating layer embedded within the semiconductor substrate and defining an active region;
a channel region formed in the active region;
a gate electrode disposed above the channel region;
a gate insulating layer provided between the channel region and the gate electrode;
a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order; and
a silicon capping layer and an etch stopping layer,
wherein the silicon capping layer and etch stopping layer are sequentially disposed on the silicon germanium epitaxial layer.

2. The semiconductor device of claim 1 , wherein the silicon germanium epitaxial layer further includes a buffer epitaxial layer having a germanium concentration lower than the first concentration, below the first epitaxial layer.

3. The semiconductor device of claim 2 , wherein the germanium concentration of the buffer epitaxial layer is in a range of 10 at % to 25 at %.

4. The semiconductor device of claim 1 , wherein the first concentration is in a range of 25 at % to 50 at %, the second concentration is in a range of 50 at % to 90 at %, and the third concentration is in a range of 25 at % to 50 at %.

5. The semiconductor device of claim 1 , further comprising: a contact plug disposed on the silicon germanium epitaxial layer,
wherein the contact plug extends into the third epitaxial layer.

6. The semiconductor device of claim 5 , further comprising: a metal silicide layer disposed between the silicon germanium epitaxial layer and the contact plug,
wherein the metal silicide layer is positioned in an upper portion of the second epitaxial layer.

7. The semiconductor device of claim 1 , wherein the active region includes a recessed region in a location corresponding to both sides of the gate electrode, and the silicon germanium epitaxial layer is formed in the recessed region of the active region.

8. The semiconductor device of claim 1 , wherein the active region includes a plurality of active layers, and the device isolating layer is provided to fill a space between the plurality of active layers to a predetermined height,
a width of the active region is reduced in an upward direction and an upper portion of the active region protrudes upwardly above the device isolating layer.

9. The semiconductor device of claim 1 , wherein the gate insulating layer includes at least one high-k dielectric layer and the gate electrode is at least comprised of one of metal silicide and a metal.

10. The semiconductor device of claim 1 , further comprising:
a contact plug disposed on the silicon germanium epitaxial layer,
wherein the contact plug extends into the silicon capping layer; and
a metal silicide layer disposed between the bottom surface of the third epitaxial layer and the contact plug.

11. A semiconductor device comprising:
a semiconductor substrate;
a device isolating layer on the semiconductor substrate defining an active region;
a channel region formed in the active region;
a gate electrode disposed above the channel region;
a gate insulating layer provided between the channel region and the gate electrode;
a silicon germanium epitaxial source/drain region adjacent to the channel region including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer on the first epitaxial layer containing a second concentration of germanium higher than the first concentration, and a third epitaxial layer on the second epitaxial layer containing a third concentration of germanium lower than the second concentration;
a contact plug disposed on the silicon germanium epitaxial source/drain region; and
a metal silicide layer disposed between the silicon germanium epitaxial source/drain region and the contact plug,
wherein the contact plug extends into the third epitaxial layer,
wherein the metal silicide layer contacts the second epitaxial layer.

12. The semiconductor device of claim 11 , wherein the silicon germanium epitaxial source/drain region further includes a buffer epitaxial layer located in a region directly below the first epitaxial layer and having a germanium concentration lower than the first concentration.

13. The semiconductor device of claim 11 , wherein the second concentration is between one and four times greater than the each of the first and third concentrations, and
wherein the first and third concentrations are different.

14. The semiconductor device of claim 12 ,
wherein the first concentration is between one and five times greater than the germanium concentration of the buffer epitaxial layer, and
wherein the second concentration is between one and four times greater than each of the first and third concentrations and between two and ten times greater than the germanium concentration of the buffer epitaxial layer.

15. The semiconductor device of claim 11 , wherein a bottom portion of the contact plug has a serrated shape corresponding to an upper surface of the silicon germanium epitaxial source/drain region.

16. The semiconductor device of claim 11 , wherein the silicon germanium epitaxial source/drain region is doped with a p-type impurity and a concentration of the p-type impurity is varied in correlation to the concentration of germanium of the first, second and third epitaxial layers of the silicon germanium epitaxial source/drain region.

17. The semiconductor device of claim 11 , wherein the silicon germanium epitaxial source/drain region further comprises:
a first interfacial layer disposed below the first epitaxial layer;
a second interfacial layer disposed between the first epitaxial layer and the second epitaxial layer; and
a third interfacial layer disposed between the second epitaxial layer and the third epitaxial layer.

18. A semiconductor device comprising:
a first active fin forming a first active region, the first active fin including at least a first channel region and being doped with an n-type impurity;
a gate electrode disposed above said first channel region and crossing said first active fin;
a gate insulating layer provided between said first channel region and the gate electrode; and
a first silicon germanium epitaxial source/drain region adjacent to said first channel region of said first active fin and doped with a p-type impurity,
wherein the first silicon germanium epitaxial source/drain region includes a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration and higher than the first concentration,
wherein the first to third epitaxial layers are sequentially stacked on one another in that order and the third epitaxial layer is the uppermost layer of the first silicon germanium epitaxial source/drain region.

19. The semiconductor device of claim 18 , wherein the first silicon germanium epitaxial source/drain region further includes a buffer epitaxial layer having a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Nam Kyu
• Suh Dong Chan
• Lee Kwan Heum
• Lee Byeong Chan
• Lee Cho Eun
• Jung Su Jin
• Kim Gyeom
• Yoon Ji Eon

Classifications

• H01L29/41766

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/7848 Primary

  Electricity · mapped topic

• H01L29/7834

  Electricity · mapped topic