Silicon germanium p-channel FinFET stressor structure and method of making same

Patent metadata

Field	Value
Publication number	US-9793404-B2
Application number	US-201514954299-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Nov 30, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.

First claim

What is claimed is:

1. A method of forming source/drain (S/D) structures for a finFET, comprising:
forming a fin on a semiconductor substrate, the fin extending above a top surface of an adjacent isolation structure;
forming a gate stack on the fin, the gate stack having a first sidewall and a second sidewall;
forming a first sidewall spacer adjacent the first sidewall, and a second sidewall spacer adjacent the second sidewall;
etching portions of the fin not covered by the gate stack and not covered by the sidewall spacers;
epitaxially growing SiGe on the etched portions of the fin; and
epitaxially growing Ge on the epitaxially grown SiGe, wherein the epitaxially grown Ge does not contact the adjacent isolation structure,
wherein the epitaxially grown SiGe has sloped surfaces, and the epitaxially grown Ge has a rounded surface.

2. The method of claim 1 , further comprising: forming a capping layer over the epitaxially grown Ge.

3. The method of claim 1 , wherein the epitaxially grown SiGe includes between 20% and 50% Ge.

4. The method of claim 1 , wherein the epitaxially grown Ge includes between 50% and 100% Ge.

5. The method of claim 1 , wherein the forming the first sidewall spacer and the second sidewall spacer comprises etching an insulating material, wherein the etching also forms sidewall spacer portions on sidewalls of the fin.

6. A method of applying compressive stress to a channel region of a p-channel finFET, comprising:
forming a gate stack on a fin, the gate stack having a first sidewall and a second sidewall, the fin extending above a top surface of an adjacent isolation structure;
forming a first sidewall spacer along the first sidewall and a second sidewall spacer along the second sidewall;
etching portions of the fin not covered by the gate stack or the sidewall spacers to provide source/drain (S/D) foundation structures;
epitaxially growing SiGe on the S/D foundation structures to form a diamond-shaped structure on each of the S/D foundation structures;
epitaxially growing Ge on each of the diamond-shaped structures to form a rounded structure, wherein the epitaxially grown Ge does not contact the adjacent isolation structure; and
forming a capping layer on each of the rounded structures.

7. The method of claim 6 , wherein a first one of the SiGe diamond-shaped structures together with a first one of the Ge rounded structures grown at a first end of the channel region, and a second one of the SiGe diamond-shaped structures together with a second one of the Ge rounded structures grown at a second end of the channel region provide compressive stress to the channel region.

8. The method of claim 7 , wherein forming the gate stack comprises forming a gate dielectric on the fin, and forming a gate electrode over the gate dielectric.

9. The method of claim 6 , wherein the capping layer comprises Si.

10. The method of claim 6 , wherein the forming the first sidewall spacer and the second sidewall spacer comprises etching an insulating material, wherein the etching also forms sidewall spacer portions on sidewalls of the fin.

11. The method of claim 6 , wherein the epitaxially grown SiGe includes between 20% and 50% Ge.

12. The method of claim 6 , wherein the epitaxially grown Ge includes between 50% and 100% Ge.

13. A method of fabricating a semiconductor device, comprising:
forming a fin on a semiconductor substrate;
forming a gate stack on the fin, the gate stack having a sidewall, the fin extending above a top surface of an adjacent isolation structure;
forming a sidewall spacer adjacent the sidewall;
etching portions of the fin not covered by the gate stack and not covered by the sidewall spacer;
epitaxially growing SiGe on the etched portions of the fin; and
epitaxially growing Ge on the epitaxially grown SiGe, wherein the epitaxially grown Ge does not contact the adjacent isolation structure,
wherein the epitaxially grown SiGe has sloped surfaces, and the epitaxially grown Ge has a rounded surface.

14. The method of claim 13 , further comprising: forming a capping layer over the epitaxially grown Ge.

15. The method of claim 14 , wherein the capping layer comprises Si.

16. The method of claim 13 , wherein the epitaxially grown SiGe includes between 20% and 50% Ge.

17. The method of claim 13 , wherein the epitaxially grown Ge includes between 50% and 100% Ge.

18. The method of claim 13 , wherein the forming the sidewall spacer comprises etching an insulating material, wherein the etching also forms sidewall spacer portions on a sidewall of the fin.

19. The method of claim 13 , wherein the SiGe on the etched portions of the fin and the Ge epitaxially grown on the SiGe provide compressive stress to the fin.

20. The method of claim 13 , wherein the forming the gate stack comprises forming a gate dielectric on the fin, and forming a gate electrode over the gate dielectric.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sung Hsueh-Chang
• Chen Liang-Yi

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H01L29/7848

  Electricity · mapped topic