Method and apparatus for duty-cycle correction in a serial data transmitter

Patent metadata

Field	Value
Publication number	US-10699669-B2
Application number	US-201816057037-A
Country	US
Kind code	B2
Filing date	Aug 7, 2018
Priority date	Mar 2, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

First claim

What is claimed is:

1. A circuit, comprising:
a serial data transmitter having a data input, a clock input, and an output;
a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter; and
a duty cycle detection circuit, connected to the output of the serial data transmitter,
the pattern generator being configured to produce a pattern comprising a plurality of sequences, each sequence including an odd number of consecutive zeros and a same odd number of consecutive ones,
the serial data transmitter being configured to transmit, during each half cycle of a double data rate clock received at the clock input of the serial data transmitter, a respective bit received at the data input of the serial data transmitter, and
the duty cycle detection circuit being configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

2. The circuit of claim 1 , wherein the duty cycle detection circuit has a clock input and comprises:
a capacitor;
a switched charge pump; and
a clocked comparator,
the switched charge pump being configured:
to charge the capacitor when the output of the serial data transmitter is in a first state and
to discharge the capacitor when the output of the serial data transmitter is in a second state,

the clocked comparator being configured to compare a voltage on the capacitor and a reference voltage, at a sampling time defined by a transition in a clock signal at the clock input of the duty cycle detection circuit.

3. The circuit of claim 1 , further comprising a multiplexer having a first input, a second input, and an output,
wherein the pattern generator is connected to the first input of the multiplexer, and the serial data transmitter is connected to the output of the multiplexer.

4. The circuit of claim 3 , further comprising a duty cycle correction circuit having an adjusted clock output connected to the clock input of the serial data transmitter, the duty cycle correction circuit being configured:
to receive:
a clock signal, and
a duty cycle correction code; and

to produce, at the adjusted clock output, an adjusted clock signal, the adjusted clock signal having a duty cycle adjusted according to the duty cycle correction code.

5. The circuit of claim 4 , further comprising a finite state machine circuit, configured:
to reset the duty cycle detection circuit;
to set the multiplexer to connect the pattern generator to the data input of the serial data transmitter;
to command the pattern generator to generate a first pattern; and
to generate a first duty cycle correction code based on one or more bits received from the duty cycle detection circuit.

6. The circuit of claim 5 , wherein the finite state machine circuit comprises a counter configured:
to count up when a bit received from the duty cycle detection circuit has a first value, and
to count down when a bit received from the duty cycle detection circuit has a second value, different from the first value.

7. The circuit of claim 5 , wherein the finite state machine circuit is further configured:
to command the pattern generator to generate a second pattern;
to generate a second duty cycle correction code based on one or more bits received from the duty cycle detection circuit; and
to feed, to the duty cycle correction circuit, a third duty cycle correction code, the third duty cycle correction code being an average of:
the first duty cycle correction code, and
the second duty cycle correction code.

8. The circuit of claim 4 , wherein the duty cycle correction circuit comprises an inverter having a programmable pull-up strength or a programmable pull-down strength.

9. A circuit, comprising:
a serial data transmitter having a data input, a clock input, and an output;
a clock source; and
a duty cycle detection and correction circuit comprising a pattern generator configured to produce a pattern comprising a plurality of sequences, each sequence including an odd number of consecutive zeros and a same number of consecutive ones,
the serial data transmitter being configured to transmit, during each half cycle of a double data rate clock received at the clock input of the serial data transmitter, a respective bit received at the data input of the serial data transmitter,
the duty cycle detection and correction circuit being configured:
to estimate, from a signal at the output of the serial data transmitter when the pattern is fed to the data input of the serial data transmitter, an error in a duty cycle of a clock embedded in the signal at the output of the serial data transmitter, and
to form an adjusted clock signal from a clock signal produced by the clock source, the adjusted clock signal having a duty cycle adjusted to reduce the error.

10. The circuit of claim 9 , wherein the duty cycle detection and correction circuit further comprises a duty cycle detection circuit connected to the output of the serial data transmitter,
wherein:
the pattern generator has a pattern data output configured to be selectively connected to the data input of the serial data transmitter; and
the duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

11. The circuit of claim 10 , wherein the duty cycle detection circuit has a clock input and comprises:
a capacitor;
a switched charge pump; and
a clocked comparator,
the switched charge pump being configured:
to charge the capacitor when the output of the serial data transmitter is in a first state and
to discharge the capacitor when the output of the serial data transmitter is in a second state,

the clocked comparator being configured to compare a voltage on the capacitor and a reference voltage, at a sampling time defined by a transition in a clock signal at the clock input of the duty cycle detection circuit.

12. The circuit of claim 10 , further comprising a multiplexer having a first input, a second input, and an output,
wherein the pattern generator is connected to the first input of the multiplexer, and the serial data transmitter is connected to the output of the multiplexer.

13. The circuit of claim 12 , further comprising a duty cycle correction circuit having an adjusted clock output connected to the clock input of the serial data transmitter, the duty cycle correction circuit being configured:
to receive:
a clock signal, and
a duty cycle correction code; and

to produce, at the adjusted clock output, an adjusted clock signal, the adjusted clock signal having a duty cycle adjusted according to the duty cycle correction code.

14. The circuit of claim 13 , further comprising a finite state machine circuit, configured:
to reset the duty cycle detection circuit;
to set the multiplexer to connect the pattern generator to the data input of the serial data transmitter;
to command the pattern generator to generate a first pattern; and
to generate a first duty cycle correction code based on one or more bits received from the duty cycle detection circuit.

15. The circuit of claim 14 , wherein t

Assignees

• Samsung Display Co Ltd

Inventors

• Amirkhany Amir
• Hekmat Mohammad

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K5/153

  Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant (switching at zero crossing H03K17/13) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• G09G5/008 Primary

  Clock recovery · CPC title