Apparatus and method for offset cancellation in duty cycle corrections

Patent metadata

Field	Value
Publication number	US-9413339-B2
Application number	US-201414290894-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	Oct 3, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

An electronic device includes a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to: assign and store a first duty cycle correction code in response to the first clock signal; assign and store a second duty cycle correction code in response to the second clock signal; calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.

First claim

What is claimed is:

1. An electronic device comprising:
a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; and
a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to:
select the first clock signal;
assign and store a first duty cycle correction code in response to the first clock signal;
select the second clock signal after the assigning and storing of the first duty cycle correction code;
assign and store a second duty cycle correction code in response to the second clock signal;
calculate an offset code based on the first and second duty cycle correction codes; and
negate the offset code from results of duty cycle correction operations.

2. The electronic device of claim 1 , wherein the duty cycle corrector is further configured to calculate the offset code by averaging the first and second duty cycle correction codes.

3. The electronic device of claim 2 , further comprising a multiplexer coupled between the clock and the duty cycle corrector, the multiplexer being configured to selectively output the first clock signal or the second clock signal.

4. The electronic device of claim 3 , further comprising a finite state machine configured to control the multiplexer to sequentially output the first clock signal and the second clock signal to the duty cycle corrector.

5. The electronic device of claim 1 , wherein the clock is further configured to retransmit the first and second clock signals.

6. The electronic device of claim 5 , wherein the duty cycle corrector is further configured to:
assign and store a third duty cycle correction code in response to the retransmitted first clock signal;
assign and store a fourth duty cycle correction code in response to the retransmitted second clock signal;
average the first and third duty cycle correction codes to obtain a first averaged duty cycle correction code;
average the second and fourth duty cycle correction codes to obtain a second averaged duty cycle correction code; and
calculate the offset code based on the first and second averaged duty cycle correction codes.

7. The electronic device of claim 6 , wherein the duty cycle corrector is further configured to calculate the offset code by averaging the first and second averaged duty cycle correction codes.

8. The electronic device of claim 1 , further comprising a finite state machine, wherein the finite state machine is configured to store therein a plurality of duty cycle correction codes corresponding to respective magnitudes of duty cycle correction.

9. An electronic device comprising:
a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device;
a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to:
assign and store a first duty cycle correction code in response to the first clock signal;
assign and store a second duty cycle correction code in response to the second clock signal;
calculate an offset code based on the first and second duty cycle correction codes; and
negate the offset code from results of duty cycle correction operations, and

a finite state machine,
wherein the finite state machine is configured to store therein a plurality of duty cycle correction codes corresponding to respective magnitudes of duty cycle correction, and
wherein a relationship between the plurality of the duty cycle correction codes and the magnitudes of duty cycle correction is linear.

10. The electronic device of claim 1 , wherein the first clock signal is a complement of the second clock signal.

11. A method of compensating for offset of a duty cycle correction loop, the method comprising:
transmitting a first clock signal to a duty cycle corrector;
transmitting a second clock signal to the duty cycle corrector;
select the first clock signal;
assigning and storing a first duty cycle correction code in response to the first clock signal;
select the second clock signal after the assigning and storing of the first duty cycle correction code;
assigning and storing a second duty cycle correction code in response to the second clock signal;
calculating an offset code based on the first and second duty cycle correction codes; and
negating the offset code from results of duty cycle correction operations.

12. The method of claim 11 , wherein the calculating the offset code comprises averaging the first and second duty cycle correction codes.

13. The method of claim 12 , wherein the transmitting the first and second clock signals comprises selectively transmitting the first clock signal or the second clock signal.

14. The method of claim 13 , wherein the transmitting the first and second clock signals comprises sequentially outputting the first clock signal and the second clock signal to the duty cycle corrector.

15. A method of compensating for offset of a duty cycle correction loop, the method comprising:
transmitting a first clock signal to a duty cycle corrector;
transmitting a second clock signal to the duty cycle corrector;
assigning and storing a first duty cycle correction code in response to the first clock signal;
assigning and storing a second duty cycle correction code in response to the second clock signal;
calculating an offset code based on the first and second duty cycle correction codes; and
negating the offset code from results of duty cycle correction operations;
retransmitting the first clock signal;
retransmitting the second clock signal;
assigning and storing a third duty cycle correction code in response to the retransmitted first clock signal;
assigning and storing a fourth duty cycle correction code in response to the retransmitted second clock signal;
averaging the first and third duty cycle correction codes to obtain a first averaged duty cycle correction code;
averaging the second and fourth duty cycle correction codes to obtain a second averaged duty cycle correction code; and
calculating the offset code based on the first and second averaged duty cycle correction codes.

16. The method of claim 15 , wherein the calculating the offset code comprises averaging the first and second averaged duty cycle correction codes.

17. The method of claim 11 , wherein a finite state machine is configured to store therein a plurality of duty cycle correction codes corresponding to respective magnitudes of duty cycle correction.

18. The method of claim 17 , wherein a relationship between the plurality of the duty cycle correction codes and the magnitudes of duty cycle correction is linear with respect to a mid-point.

19. The method of claim 11 , wherein the first clock signal is a complement of the second clock signal.

20. The method of claim 11 , wherein the method is performed in an electronic device and is repeated periodically during operation of the electronic device.

Assignees

• Samsung Display Co Ltd

Inventors

• Amirkhany Amir
• Hekmat Mohammad

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title