Memory components and controllers that calibrate multiphase synchronous timing references

Patent metadata

Field	Value
Publication number	US-2016343418-A1
Application number	US-201615228644-A
Country	US
Kind code	A1
Filing date	Aug 4, 2016
Priority date	Apr 22, 2011
Publication date	Nov 24, 2016
Grant date	—

Abstract

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

First claim

What is claimed is:

1 . A memory device, comprising:
a first circuit to receive a first external timing reference signal; a second circuit to receive a second external timing reference signal, the second external timing reference signal to have approximately a quadrature phase relationship with respect to the first external timing reference signal, the approximately quadrature phase relationship having first, second, third, and fourth transitions and, a plurality of sampler circuits, each one of the sampler circuits of the plurality of sampler circuits to be triggered based on one of the first, second, third, and fourth transitions, respectively, the plurality of sampler circuits each to resolve a plurality of signal values, each of the plurality of signal values to be associated with one of the first, second, third, and fourth transitions, respectively; and, a third circuit to send the plurality of signal values to a source of the first timing reference signal and the second timing reference signal.

2 . The memory device of claim 1 , wherein the source is to determine a first duty cycle adjustment of a first internal timing reference signal, the first duty cycle adjustment based on at least a first plurality of the plurality of signal values associated with the first transition and a second plurality of the plurality of signal values associated with the second transition.

3 . The memory device of claim 2 , further comprising:
a fourth circuit to receive the first duty cycle adjustment sent by the source.

4 . The memory device of claim 2 , wherein the source is to determine a quadrature phase adjustment of a second internal timing reference signal in relation to the first internal timing reference signal based on at least the first plurality of the plurality of signal values associated with the first transition and a third plurality of the plurality of signal values associated with the third transition.

5 . The memory device of claim 4 , further comprising:
a fifth circuit to receive the quadrature phase adjustment sent by the source.

6 . The memory device of claim 4 , wherein the source is to determine a second duty cycle adjustment of the second internal timing reference signal based on at least the third plurality of the plurality of signal values associated with the third transition and a fourth plurality of the plurality of signal values associated with the fourth transition.

7 . The memory device of claim 3 , wherein the first duty cycle adjustment is a global adjustment.

8 . The memory device of claim 3 , wherein the first duty cycle adjustment is a local adjustment.

9 . A method of calibrating, comprising:
receiving a first external timing reference signal; receiving a second external timing reference signal, the second external timing reference signal to have approximately a quadrature phase relationship with respect to the first external timing reference signal, the approximately quadrature phase relationship having first, second, third, and fourth transitions and, receiving a plurality of signal values from a plurality of sampler circuits, each one of the sampler circuits of the plurality of sampler circuits to be triggered based on one of the first, second, third, and fourth transitions, respectively, the plurality of sampler circuits each to resolve at least one of the plurality of signal values, each of the plurality of signal values to be associated with one of the first, second, third, and fourth transitions, respectively; and, sending the plurality of signal values to a source of the first timing reference signal and the second timing reference signal.

10 . The method of claim 9 , wherein the source is to determine a first duty cycle adjustment of a first internal timing reference signal, the first duty cycle adjustment based on at least a first plurality of the plurality of signal values associated with the first transition and a second plurality of the plurality of signal values associated with the second transition.

11 . The method of claim 10 , further comprising:
a fourth circuit to receive the first duty cycle adjustment sent by the source.

12 . The method of claim 10 , wherein the source is to determine a quadrature phase adjustment of a second internal timing reference signal in relation to the first internal timing reference signal based on at least the first plurality of the plurality of signal values associated with the first transition and a third plurality of the plurality of signal values associated with the third transition.

13 . The method of claim 12 , further comprising:
a fifth circuit to receive the quadrature phase adjustment sent by the source.

14 . The method of claim 12 , wherein the source is to determine a second duty cycle adjustment of the second internal timing reference signal based on at least the third plurality of the plurality of signal values associated with the third transition and a fourth plurality of the plurality of signal values associated with the fourth transition.

15 . A memory controller, comprising:
a first circuit to send a first external timing reference signal to a memory device; a second circuit to send a second external timing reference signal to the memory device, the second external timing reference signal to have approximately a quadrature phase relationship with respect to the first external timing reference signal, the approximately quadrature phase relationship having first, second, third, and fourth transitions; and, a third circuit to receive a plurality of signal values from the memory device, each of the plurality of signal values to be associated with one of the first, second, third, and fourth transitions, respectively, the plurality of signal values to be resolved by a plurality of sampler circuits of the memory device, each one of the sampler circuits of the plurality of sampler circuits to be triggered based on one of the first, second, third, and fourth transitions, respectively.

16 . The memory controller of claim 15 , further comprising:
a fourth circuit to determine a first duty cycle adjustment of a first timing reference signal internal to the memory device, the first duty cycle adjustment based on at least a first plurality of the plurality of signal values associated with the first transition and a second plurality of the plurality of signal values associated with the second transition.

17 . The memory controller of claim 16 , further comprising:
a fifth circuit to send the first duty cycle adjustment to the memory device.

18 . The memory controller of claim 16 , further comprising:
a fifth circuit to determine a quadrature phase adjustment of a second timing reference signal internal to the memory device in relation to the first timing reference signal internal to the memory device, the quadrature phase adjustment based on at least the first plurality of the plurality of signal values associated with the first transition and a third plurality of the plurality of signal values associated with the third transition.

19 . The memory controller of claim 18 , further comprising:
a fifth circuit to send the quadrature phase adjustment to the memory device.

20 . The memory controller of claim 17 , wherein the first duty cycle adjustment is a global adjustment.

Assignees

• Rambus Inc

Inventors

• Giovannini Thomas
• Best Scott
• Luo Lei
• Shaeffer Ian

Classifications

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/227

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title