Duty cycle distortion correction circuitry

Patent metadata

Field	Value
Publication number	US-9048823-B2
Application number	US-201313930662-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Nov 14, 2011
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

First claim

What is claimed is:

1. A circuit, comprising:
an input that receives a control signal having a duty cycle;
an output on which an output clock signal is generated, wherein the output clock signal has an adjustable duty cycle that is different than the duty cycle of the control signal; and
an additional input that receives an additional control signal, wherein the control signal is a delayed version of the additional control signal, and wherein the control signal is delayed by an amount with respect to the additional control signal that sets the adjustable duty cycle of the output clock signal.

2. The circuit defined in claim 1 , wherein the control signal received at the input comprises an input clock signal.

3. The circuit defined in claim 1 , wherein the adjustable duty cycle of the output clock signal is greater than the duty cycle of the control signal.

4. The circuit defined in claim 1 , further comprising:
a second additional input that receives a second additional control signal, wherein the output clock signal is generated using the control signal, the additional control signal, and the second additional control signal.

5. The circuit defined in claim 1 , further comprising:
a second additional input that receives an enable signal, wherein the circuit is switched out of use when the enable signal has a first value, and wherein the circuit is switched into use when the enable signal has a second value.

6. The circuit defined in claim 1 ,
wherein the control signal and the additional control signal have transition edges that determine the adjustable duty cycle of the output clock signal.

7. A method for operating a circuit to generate an output clock signal, comprising:
receiving first and second control signals;
in response to detecting a transition edge in the first control signal, asserting the output clock signal; and
in response to detecting a transition edge in the second control signal, deasserting the output clock signal, wherein the first and second control signals and the output clock signal exhibit the same frequency.

8. The method defined in claim 7 , wherein receiving the first and second control signals comprises receiving first and second input clock signals.

9. The method defined in claim 7 , wherein receiving the first and second control signals comprises receiving first and second input clock signals, and wherein the output clock signal has a duty cycle that is set by an amount by which the second control signal is delayed with respect to the first control signal.

10. The method defined in claim 7 , further comprising:
receiving a third control signal;
asserting and deasserting the output clock signal only when the third control signal is asserted.

11. The method defined in claim 10 , wherein the third control signal is delayed with respect to the first control signal by a first phase offset.

12. The method defined in claim 11 , wherein the second control signal is delayed with respect to the first control signal by a second phase offset that is greater than the first phase offset.

13. The method defined in claim 7 , wherein the output clock signal has a duty cycle, the method further comprising:
adjusting the duty cycle of the output clock signal by controlling the second control signal.

14. The method defined in claim 7 , wherein receiving the first control signal comprises receiving an input clock signal having a given duty cycle, the method further comprising:
generating the output clock signal with a corrected duty cycle that is different than the given duty cycle of the input clock signal.

15. Circuitry comprising:
a clock generation circuit that outputs at least first and second clock signals;
a first buffer circuit having an input that receives the first clock signal and an output on which a first output clock signal is generated, wherein the first output clock signal has a duty cycle that is set by the first clock signal; and
a second buffer circuit having an input that receives the second clock signal and an output on which a second output clock signal is generated, wherein the second output clock signal has a duty cycle that is set by the second clock signal, wherein the first and second clock signals exhibit first and second duty cycles, and wherein the duty cycle of the first output clock signal is identical to the duty cycle of the second output clock signal but is different than the first and second duty cycles.

16. The circuitry defined in claim 15 , wherein the clock generation circuit further outputs third and fourth clock signals, wherein the first buffer circuit further includes a first additional input that receives the third clock signal, and wherein the second buffer circuit further includes a first additional input that receives the fourth clock signal.

17. The circuitry defined in claim 16 , wherein the first buffer circuit further includes a second additional input that receives the fourth clock signal, and wherein the second buffer circuit further includes a second additional input that receives the first clock signal.

18. The circuitry defined in claim 16 , wherein the first clock signal is delayed with respect to the third clock signal by a first amount of delay, and wherein the duty cycle of the first output clock signal is determined by the first amount of delay.

19. The circuitry defined in claim 16 , wherein the first, second, third, and fourth clock signals have identical duty cycles that are different than the duty cycles of the first and second output clock signals.

Assignees

• Altera Corp

Inventors

• Bui John Henry
• Khoo Lay Hock
• Nguyen Khai
• Sung Chiakang
• Sia Ket Chiew

Classifications

• H03K19/018592

  with a bidirectional operation · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K19/09429

  one of the states being the high impedance or floating state · CPC title