Calibration of sampling phase and aperature errors in multi-phase sampling systems

Patent metadata

Field	Value
Publication number	US-9369263-B1
Application number	US-201514788192-A
Country	US
Kind code	B1
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.

First claim

What is claimed is:

1. A method of calibrating sampling phases of a multi-phase sampling system, the method comprising:
generating at least one phase reference pattern signal on-chip by a reference pattern generator circuit;
correcting for a duty cycle distortion (DCD) of said at least one on-chip phase reference pattern signal, said at least one DCD corrected on-chip reference pattern signal being input to a data path, said data path providing at least one reference output pattern signal;
sampling, using a sampling circuit responsive to a sampling clock signal, said at least one reference output pattern signal to take samples; and
modifying a phase of said clock signal to align the samples taken by said sampling circuit of said at least one reference output pattern signal to edges thereof.

2. The method of claim 1 , further comprising:
periodically inverting the on-chip generated phase reference pattern signal within the reference pattern generator circuit, and performing a clock phase correction before and after the inverting with averaging phase correction result values to cancel out errors due to a duty cycle distortion (DCD) in the at least one reference output pattern signal.

3. The method of claim 2 , wherein performing the clock phase correction comprises:
detecting a convergence to a first pattern edge to obtain a first phase correction result value prior to said reference pattern signal inverting, and
detecting a second convergence to an inverted version of the first pattern edge to obtain a second phase correction result value after said reference pattern signal inverting; and
averaging said first and second phase correction result values.

4. The method of claim 1 , further comprising:
outputting the sampling clock signal from an electronic phase rotator device for said sampling said at least one reference output pattern signal from said data path, said modifying including:
determining whether a latch of the sampling circuit is sampling before or after a zero-crossing; and, in response to said determining,
adjusting, using a phase calibration logic, a phase sampling calibration of said sampling clock signal to align its sample to the zero crossing.

5. The method of claim 4 , wherein said adjusting phase sampling calibration of said sampling clock signal comprises:
controlling, using a processor device configured with said phase calibration logic, a respective digital-to-analog conversion (DAC) device for adjusting a phase of said sampling clock signal output received from said electronic phase rotator device.

6. The method of claim 1 , wherein said on-chip generated phase reference pattern signal is a differential signal pair of reference pattern signals, each received at a respective input of a respective signal path, said correcting for said DCD comprising:
sensing, using a low pass filter, each said on-chip generated reference pattern signal to obtain a first average voltage level (Vpavg)) and a second average voltage level (Vnavg), said first Vpavg corresponding to a first signal of said differential pair and said second Vnavg corresponding to a second signal of said differential pair;
comparing, using a comparator circuit, a difference between said Vpavg and said Vnavg signals; and
responsive to said comparing, adjusting a setting of a respective digital-to-analog converter device located in each respective signal path associated with a respective signal of said differential pair of reference pattern signals.

7. The method of claim 2 , wherein said on-chip generated phase reference pattern signal is a differential signal pair of reference pattern signals received at inputs of a respective signal path, each respective signal path including a respective pre-inverting digital-to-analog converter (pre-dac) device, said method correcting for said duty cycle distortion (DCD) comprising:
inputting each received reference pattern signal from respective pre-dac device outputs to a flip-multiplexor device configured to invert said on-chip generated phase reference pattern differential signals;
sensing, using a low pass filter, a non-inverted reference pattern signal output of said flip-multiplexor device, to obtain a first average voltage level (Vpavg)) and a second average voltage level (Vnavg), said first Vpavg corresponding to a first signal of said differential pair and said second Vnavg corresponding to a second signal of said differential pair;
comparing, using a comparator circuit, a difference between said first Vpavg and said second Vnavg signals; and
responsive to said comparing, correcting for said DCD error by adjusting a setting of a respective pre-inverting digital-to-analog converter (pre-dac) device located in each signal path;
storing a first pre-inverting dac setting when said DCD error is corrected;
inverting the received reference pattern signals through the flip-multiplexor device;
sensing, using a low pass filter, each said on-chip generated reference pattern signal output of said flip-multiplexor device to obtain a further first average voltage level (Vpavg)) and a further second average voltage level (Vnavg) for a respective signal of said differential pair;
comparing, using a comparator circuit, a difference between said further first Vpavg and said further second Vnavg signals; and
responsive to said comparing, correcting for said DCD error by adjusting a setting of a respective digital-to-analog converter (pre-dac) device located in each signal path;
storing a second pre-inverting dac setting when said DCD error is corrected;
averaging said first and second pre-inverting dac settings; and
setting each respective said pre-inverting digital-to-analog converter device using said average.

8. The method of claim 7 , wherein a signal path of each signal of said differential pair at an output of the flip-multiplexor device path includes a corresponding post-inverting digital-to-analog converter (post-dac) device for receiving each respective reference pattern signal through the flip-multiplexor device, said correcting for said DCD error comprising:
sensing, using a low pass filter, a non-inverted reference pattern signal output of said flip-multiplexor device, to obtain another first average voltage level (Vpavg)) and another second average voltage level (Vnavg), said another first Vpavg corresponding to a first signal of said differential pair and said another second Vnavg corresponding to a second signal of said differential pair;
comparing, using a comparator circuit, a difference between said another first Vpavg and said another second Vnavg signals; and
responsive to said comparing, correcting for said DCD error by adjusting a setting of a respective post-inverting digital-to-analog converter (post-dac) device located in each corresponding signal path; and
storing a first post-inverting dac setting when said DCD error is corrected;
inverting the received reference pattern signals through the flip-multiplexor device;
sensing, using a low pass filter, each said reference pattern signal output of said flip-multiplexor device to obtain another further first average voltage level (Vpavg) and another further second average voltage level (Vnavg) for a respective signal of said differential pair;
comparing, using a comparator circuit, a difference between said another further first Vpavg and said another further second Vnavg signals; and
responsive to said comparing, adjusting a setting of a respective digital-to-analog converter (post-dac) device;
storing a second post-inverting dac setting when said DCD error is corrected; and
averaging said first and second post-inverting dac setting values; and
setting each respective said post-inverting digital-to-analog converter device using said

Assignees

• IBM

Inventors

• Baecher Matthew B
• Bulzacchelli John F
• Ewen John F
• Gangasani Gautam
• Meghelli I Mounir
• Paschal Matthew J
• Shah Trushil N

Classifications

• H04B17/21 Primary

  for calibration; for correcting measurements · CPC title

• H04L7/0025 Primary

  interpolation of clock signal · CPC title

• H04L7/06

  the synchronisation signals differing from the information signals in amplitude, polarity or frequency {or length} · CPC title

• H04L1/24

  Testing correct operation · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title