Stud bumps for post-measurement qubit frequency modification

Patent metadata

Field	Value
Publication number	US-10692831-B1
Application number	US-201916281770-A
Country	US
Kind code	B1
Filing date	Feb 21, 2019
Priority date	Feb 21, 2019
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

According to an embodiment of the present invention, a method of producing a quantum computer chip includes performing a frequency measurement on a qubit chip bonded to a test interposer chip for qubits on the qubit chip at an operating temperature of the qubit chip. The method further includes pulling the qubit chip apart from the test interposer chip after performing the frequency measurement, and modifying a frequency of a subset of qubits after pulling the qubit chip apart from the test interposer chip. The method further includes bonding the qubit chip to a device interposer chip after modifying the frequency of the subset of qubits.

First claim

What is claimed is:

1. A method of producing a quantum computer chip, comprising:
performing a frequency measurement on a qubit chip bonded to a test interposer chip for qubits on the qubit chip at an operating temperature of the qubit chip;
pulling the qubit chip apart from the test interposer chip after performing the frequency measurement;
modifying a frequency of a subset of qubits after pulling the qubit chip apart from the test interposer chip; and
bonding the qubit chip to a device interposer chip after modifying the frequency of the subset of qubits.

2. The method of claim 1 , wherein the device interposer chip is the test interposer chip reused.

3. The method of claim 1 , further comprising:
bonding the qubit chip to the test interposer chip prior to performing the frequency measurement; and
cooling the bonded qubit chip and test interposer chip to the operating temperature of the qubit chip.

4. The method of claim 3 , wherein the qubit chip comprises at least one metallic pad and a metallic stud formed on each metallic pad,
wherein the test interposer chip comprises at least one metallic pad and a test solder bump formed on each metallic pad,
wherein the device interposer chip comprises at least one metallic pad and a device solder bump formed on each metallic pad,
wherein bonding the qubit chip to the test interposer chip comprises bonding the metallic studs formed on the qubit chip to the test solder bumps formed on the test interposer chip, and
wherein bonding the qubit chip to the device interposer chip comprises bonding the metallic studs formed on the qubit chip to the device solder bumps formed on the device interposer chip.

5. The method according to claim 4 , wherein the test solder bumps contact a first area of the metallic pads on which the metallic studs are formed, and
wherein the device solder bumps contact a second area of the metallic pads on which the metallic studs are formed, at least a portion of the second area being different from the first area.

6. The method according to claim 4 , wherein the qubit chip further comprises a second metallic stud formed on each metallic pad, and the device interposer chip further comprises at least one second metallic pad and a second device solder bump formed on each second metallic pad,
the method further comprising bonding the second metallic studs formed on the qubit chip to the second device solder bumps formed on the device interposer chip.

7. The method according to claim 4 , wherein the qubit chip further comprises at least one metallic plated pillar formed on each metallic pad, and the device interposer chip further comprises at least one second metallic pad and a second device solder bump formed on each second metallic pad,
the method further comprising bonding the metallic plated pillar formed on the qubit chip to the second device solder bump formed on the device interposer chip.

8. The method of claim 4 ,
wherein the qubit chip comprises a plurality of metallic studs,
wherein the test interposer chip comprises a plurality of test solder bumps, and
wherein the device interposer chip comprises a plurality of device solder bumps.

9. The method of claim 8 , wherein the number of test solder bumps in the plurality of test solder bumps is less than the number of metallic studs in the plurality of metallic studs,
wherein the number of test solder bumps in the plurality of test solder bumps is less than the number of device solder bumps in the plurality of device solder bumps,
wherein bonding the qubit chip to the test interposer chip comprises bonding a subset of the plurality of metallic studs to the plurality of test solder bumps, and
wherein bonding the qubit chip to the device interposer chip comprises bonding the plurality of metallic studs to the plurality of device solder bumps.

10. The method of claim 9 , wherein the size of each device solder bump is larger than that of each test solder bump.

11. The method of claim 10 , wherein the device interposer chip is the test interposer chip reused, the method further comprising removing the test solder bumps from the test interposer chip after the pulling and forming the plurality of device solder bumps on the test interposer chip.

12. The method of claim 8 , wherein the qubit chip further comprises a plurality of metallic plated pillars,
wherein bonding the qubit chip to the test interposer chip comprises bonding the plurality of metallic studs to the plurality of test solder bumps, and
wherein bonding the qubit chip to the device interposer chip comprises bonding the plurality of metallic studs to a first plurality of the plurality of device solder bumps, and bonding the plurality of metallic plated pillars to a second plurality of the plurality of device solder bumps.

13. The method of claim 12 , wherein the number and size of device solder bumps are larger than the number and size of the test solder bumps.

14. The method of claim 13 , wherein the device interposer chip is the test interposer chip reused, the method further comprising removing the test solder bumps from the test interposer chip after the pulling and forming the plurality of device solder bumps on the test interposer chip.

15. The method of claim 13 , further comprising performing resistance measurements across Josephson junctions formed on the qubit chip prior to bonding the qubit chip to the test interposer chip.

16. The method of claim 13 , further comprising heating the bonded qubit chip and test interposer chip to a temperature at which the modifying the frequency can be performed.

17. A quantum computer chip produced according to the method of claim 1 .

18. The quantum computer chip according to claim 17 , wherein the qubit chip comprises at least one metallic pad and a metallic stud formed on each metallic pad,
wherein the test interposer chip comprises at least one metallic pad and a test solder bump formed on each metallic pad,
wherein the device interposer chip comprises at least one metallic pad and a device solder bump formed on each metallic pad, and
wherein the metallic studs formed on the qubit chip are bonded to the device solder bumps formed on the device interposer chip to form the quantum computer chip.

19. The quantum computer chip according to claim 18 , wherein the metallic studs are formed from a material that is not superconducting, and wherein a distance over which the device solder bumps envelope the metallic studs formed on the qubit chip is much greater than the coherence length of the device solder bumps.

20. The quantum computer chip according to claim 18 , wherein the metallic studs are formed from a material that is not superconducting, and wherein a distance over which the device solder bumps contact the metallic pads formed on the qubit chip is much greater than the coherence length of the device solder bumps.

21. The quantum computer chip according to claim 18 , wherein the test solder bump is formed from a material that is superconducting, and wherein the device solder bump is formed from a material that is superconducting.

22. The quantum computer chip according to claim 18 , wherein the qubit chip further comprises a second metallic stud formed on each metallic pad, and the device interposer chip further comprises at least one second metallic pad and a second device solder bump formed on each second metallic pad,
wherein the second metallic studs are bonded to the second device solder bumps.

23.

Assignees

• IBM

Inventors

• Bronn Nicholas T
• Hertzberg Jared B
• Lewandowski Eric P
• Nah Jae-Woong

Classifications

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/072

  of bump connectors · CPC title