Multi-plane heater for semiconductor substrate support

Patent metadata

Field	Value
Publication number	US-10690414-B2
Application number	US-201514966198-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Dec 11, 2015
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a multi-plane heater such as a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate. The multi-plane heater includes at least one pair of vertically offset heating elements connected in series or parallel to control heating output in a heating zone on the substrate support. The thermal control elements can be powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones.

First claim

What is claimed is:

1. A multi-plane heater of a semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber, the multi-plane heater comprising:
a first resistance heating element;
a second resistance heating element; and
a body of dielectric material containing the first resistance heating element and the second resistance heating element,
wherein
the first resistance heating element is vertically offset from and electrically connected in series with the second resistance heating element such that the first resistance heating element and the second resistance heating element form an individually addressable thermal control element and such that the first resistance heat element and the second resistance heat element are capable of being powered as a unitary structure without powering another resistance heat element of the multi-plane heater.

2. The multi-plane heater of claim 1 , wherein:
the first resistance heating element is located on an outer portion of a first layer of dielectric material;
the second resistance heating element is located on an outer portion of a second layer of dielectric material;
the first layer of dielectric material and the second layer of dielectric material are bonded to a third layer of dielectric material with the first resistance heating element embedded in the first layer of dielectric material and the second resistance heating element embedded in the second layer of dielectric material; and
the first resistance heating element and the second resistance heating element comprise planar resistance heaters having the same size.

3. The multi-plane heater of claim 2 , wherein:
the first resistance heating element and the second resistance heating element are on layers of dielectric ceramic material with discrete electrically resistive traces;
the discrete electrically resistive traces include the first resistance heating element and second resistance heating element;
the first layer of dielectric material and the second layer of dielectric material are bonded to at least one additional layer of dielectric material with electrically conductive vias;
the electrically conductive vias connect the first resistance heating element and the second resistance heating element in series; and
the first resistance heating element and the second resistance heating element comprise laminates of electrically resistive material encapsulated in polymeric material.

4. A semiconductor substrate support comprising:
an electrostatic clamping layer including at least one electrostatic clamping electrode, wherein the at least one electrostatic clamping electrode is configured to electrostatically clamp a semiconductor substrate on a support surface of the substrate support;
a multi-plane heater comprising a body of dielectric material, wherein the body of dielectric material includes a first resistance heating element and a second resistance heating element, wherein the first resistance heating element is vertically offset from the second resistance heating element, wherein the first resistance heating element and the second resistance heating element are electrically connected in series such that the first resistance heating element and the second resistance heating element form a first individually addressable thermal control element and such that the first resistance heat element and the second resistance heat element are capable of being powered as a unitary structure without powering another resistance heat element of the multi-plane heater; and
a temperature controlled base plate beneath the multi-plane heater.

5. The semiconductor substrate support of claim 4 , further comprising:
(a) a primary heater layer including at least one primary heating element, wherein the at least one primary heating element is configured to provide temperature control of the support surface, and wherein the multi-plane heater is located between the primary heater layer and the electrostatic clamping layer;
(b) a heater array of individually controlled resistive heating elements operable to tune a spatial temperature profile of the semiconductor substrate, wherein the multi-plane heater comprises a primary heater, which provides temperature control of the support surface of the substrate support; or
(c) the base plate receives a radio frequency signal, wherein the first resistance heating element and the second resistance heating element are arranged in a manner which minimizes a net magnetic field generated in a direction parallel to a plane of the support surface as a result of receiving the radio frequency signal.

6. The semiconductor substrate support of claim 4 , further comprising:
a third resistance heating element vertically offset from and connected in series with a fourth resistance heating element such that the third resistance heating element and the fourth resistance heating element form a second individually addressable thermal control element;
a fifth resistance heating element vertically offset from and connected in series with a sixth resistance heating element such that the fifth resistance heating element and the sixth resistance heating element form a third individually addressable thermal control element;
a seventh resistance heating element vertically offset from and connected in series with an eighth resistance heating element such that the seventh resistance heating element and the eighth resistance heating element form a fourth individually addressable thermal control element; and
power supply lines and power return lines configured to deliver power to the first individually addressable thermal control element, the second individually addressable thermal control element, the third individually addressable thermal control element and the fourth individually addressable thermal control element,
wherein
each of the power supply lines is connected to at least two of the first individually addressable thermal control element, the second individually addressable thermal control element, and the third individually addressable thermal control element,
each of the power return lines is connected to at least two of the first resistance heating element, the second resistance heating element, the third resistance heating element, the fourth resistance heating element, the fifth resistance heating element, the sixth resistance heating element, the seventh resistance heating element and the eighth resistance heating element, and
each of the first individually addressable thermal control element, the second individually addressable thermal control element, and the third individually addressable thermal control element is connected to a different pair of the power supply lines and the power return lines.

7. A multi-plane heater of a semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber, the multi-plane heater comprising:
a heater array comprising independently controlled heating elements operable to tune a spatial temperature profile on the semiconductor substrate;
the heater array including a first layer of independently controlled heating elements and a second layer of independently controlled heating elements;
the first layer of heating elements including a first group of heating elements and a second group of heating elements, wherein the first group of heating elements is vertically offset from the second group of heating elements of the second layer of heating elements; and
the heating elements of the first group of heating elements are respectively connected to the heating elements of the second group of heating elements such that each pair of vertically offset heating elements is an individually addressable thermal control element and such that

Assignees

• Lam Res Corp

Inventors

• Gaff Keith William
• Wu Benny
• Pape Eric A

Classifications

• H10P72/0432

  mainly by conduction · CPC title

• H10P72/72

  using electrostatic chucks · CPC title

• H10P72/7624

  characterised by the mechanical construction of the susceptor, stage or support · CPC title

• H10P72/0434

  mainly by convection · CPC title

• F27D5/0037

  Supports specially adapted for semi-conductors · CPC title