Air-gap top spacer and self-aligned metal gate for vertical FETs

Patent metadata

Field	Value
Publication number	US-9941378-B2
Application number	US-201715624061-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	May 11, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Methods for forming a transistor include forming a gate conductor in contact with a gate stack. The gate conductor has a top surface that meets a middle point of sidewalls of a sacrificial region of a fin. The sacrificial region of the fin is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor. The top spacer includes airgaps above the gate stack.

First claim

What is claimed is:

1. A method for forming a transistor, comprising:
forming a gate conductor in contact with a gate stack, the gate conductor having a top surface that meets a middle point of sidewalls of a sacrificial region of a fin;
trimming the sacrificial region of the fin to create gaps above the gate stack; and
forming a top spacer on the gate conductor, the top spacer including airgaps above the gate stack.

2. The method of claim 1 , further comprising forming the fin on a bottom source/drain region and forming a top source/drain region directly on a top surface of the channel region after forming the top spacer.

3. The method of claim 2 , wherein forming the fin comprises etching a stack comprising a first layer of a first semiconductor material and a second layer of a second semiconductor material to form a channel layer from the first semiconductor material and to form the sacrificial region from the second semiconductor material.

4. The method of claim 3 , wherein the first semiconductor material is silicon and the second semiconductor material is silicon germanium.

5. The method of claim 3 , further comprising forming a bottom spacer directly on the bottom source/drain region around the fin.

6. The method of claim 3 , wherein forming the fin further comprises laterally etching the channel layer to form the channel region, such that the sacrificial region overhangs sidewalls of the channel region.

7. The method of claim 1 , wherein trimming the sacrificial region comprises trimming the sacrificial region to a same width as a channel region of the fin.

8. The method of claim 1 , wherein forming the top spacer comprises a non-conformal dielectric deposition process.

9. The method of claim 1 , wherein forming the top spacer comprises forming a first dielectric layer and forming a second dielectric layer having a lower dielectric constant than the first dielectric layer.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Standaert Theodorus E
• Wang Junli

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title