High-k/metal gate transistor with L-shaped gate encapsulation layer

Patent metadata

Field	Value
Publication number	US-9252018-B2
Application number	US-201213571977-A
Country	US
Kind code	B2
Filing date	Aug 10, 2012
Priority date	Nov 18, 2009
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

First claim

What is claimed is:

1. A transistor comprising:
a silicon layer including a source region and a drain region;
a gate stack disposed on the silicon layer between the source region and the drain region, the gate stack comprising a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon;
an L-shaped gate encapsulation layer disposed on sidewalls of the gate stack, the gate encapsulation layer comprising a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack;
an L-shaped spacer layer comprising a vertical portion covering sidewalls of the vertical portion of the L-shaped gate encapsulation layer, and a horizontal portion covering the horizontal portion of the L-shaped gate encapsulation layer, where the L-shaped er is formed with a thickness that is less than a thickness of the L-shaped gate encapsulation layer;
a spacer disposed above and on the horizontal portion of the L-shaped spacer layer and adjacent to and in contact with the vertical portion of the L-shaped spacer layer, wherein the L-shaped gate encapsulation layer, the L-shaped spacer layer, and the spacer are formed with a combined width that is greater than a width of the gate stack; and
source/drain extensions in the silicon layer, the source/drain extensions not underlying the first layer of the gate stack, the source/drain extensions underlying and extending beyond part but not all of the vertical portion of the gate encapsulation layer, and the source and drain regions not underlying the first layer of the gate stack.

2. The transistor of claim 1 , wherein the gate encapsulation layer comprises nitride.

3. The transistor of claim 2 , wherein the spacer consists of a single oxide nitride layer.

4. The transistor of claim 2 , wherein the L-shaped spacer layer comprises an oxide material and the spacer comprises a nitride material.

5. The transistor of claim 2 , wherein a thickness of the gate encapsulation layer is less than a thickness of the first layer of the gate stack.

6. The transistor of claim 2 , wherein a thickness of the vertical portion of the gate encapsulation layer is substantially equal to a thickness of the horizontal portion of the gate encapsulation layer.

7. The transistor of claim 2 ,
wherein the first layer of the gate stack comprises at least one of HfO 2 , HfSiO, HfSiON, HfZrO, TiO 2 , La 2 O 3 , Y 2 O 3 , and Al 2 O 3 , and
the second layer of the gate stack comprises at least one of TiN, TaN, TaC, TiAlN, and TaAlN.

8. The transistor of claim 1 , wherein a distance between the source/drain extensions is greater than a lateral extent of the first layer of the gate stack.

9. The transistor of claim 1 ,
wherein
each of the source/drain extensions underlies part but not all of the spacer.

10. The transistor of claim 9 , wherein the source and drain regions underlie part but not all of the single layer of the spacer.

11. The transistor of claim 1 , wherein the third layer of the gate stack consists of amorphous silicon.

12. The transistor of claim 11 , further comprising a layer of silicon germanium located on the silicon layer.

13. The transistor of claim 1 , further comprising a layer of silicon germanium located between the silicon layer and the first layer of the gate stack.

14. The transistor of claim 1 , wherein the horizontal portion of the L-shaped gate encapsulation layer directly contacts the silicon layer.

15. A transistor comprising:
a silicon layer including a source region and a drain region;
a gate stack disposed on the silicon layer between the source region and the drain region, the gate stack comprising a first layer of high dielectric constant material, a second layer disposed on and in contact with the first layer, and a third layer disposed on and in contact with the second layer, the second layer comprising one or more of TaN, TaC, TiAlN, TaAlN, and the third layer comprising aluminum and being separate from the second layer;
an L-shaped gate encapsulation layer disposed on sidewalls of the gate stack, the gate encapsulation layer comprising a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack;
an L-shaped spacer layer comprising a vertical portion covering sidewalls of the vertical portion of the L-shaped a horizontal portion covering the horizontal portion of the L-shaped encapsulation layer, where the L-shaped r layer is formed with a thickness that is less than a thickness of the L-shaped gate encapsulation layer; and
a spacer disposed above and on the horizontal portion of the L-shaped spacer layer and adjacent to and in contact with the vertical portion of the L-shaped spacer layer, wherein the L-shaped gate encapsulation layer, the L-shaped spacer layer, and the spacer are formed with a combined width that is greater than a width of the gate stack.

16. The transistor of claim 15 , wherein the third layer consists of aluminum.

17. The transistor of claim 15 , further comprising a layer of silicon germanium located between the silicon layer and the first layer of the gate stack.

18. The transistor of claim 15 , further comprising source/drain extensions in the silicon layer, the source/drain extensions not underlying the first layer of the gate stack, the source/drain extensions underlying part but not all of the vertical portion of the gate encapsulation layer, and the source and drain regions not underlying the first layer of the gate stack.

19. The transistor of claim 18 , wherein a distance between the source/drain extensions is greater than a lateral extent of the first layer of the gate stack.

20. The transistor of claim 15 ,
wherein
the source and drain regions underlie part but not all of the spacer.

Assignees

• Mo Renee T
• Natzle Wesley C
• Narayanan Vijay
• Sleight Jeffrey W
• IBM

Inventors

• Mo Renee T
• Natzle Wesley C
• Narayanan Vijay
• Sleight Jeffrey W

Classifications

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title