Bumped resonator structure

Patent metadata

Field	Value
Publication number	US-10651361-B2
Application number	US-201916248981-A
Country	US
Kind code	B2
Filing date	Jan 16, 2019
Priority date	Nov 30, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A technique relates a structure. An inductive element is on a first surface. A capacitive element is on the first surface and a second surface. An interconnect structure is between the first surface and the second surface.

First claim

What is claimed is:

1. A structure comprising:
an inductive element on a first surface;
a capacitive element on the first surface and a second surface, such that an interconnect structure is positioned between the first surface and the second surface; and
a qubit on the second surface.

2. The structure of claim 1 , wherein the qubit is positioned a distance from the inductive element.

3. The structure of claim 1 , wherein the first surface and the second surface are opposite surfaces on a substrate.

4. The structure of claim 1 , wherein the first surface and the second surface are on different substrates.

5. The structure of claim 1 , wherein the qubit is on an opposite side of a substrate from the inductive element.

6. The structure of claim 1 , wherein the qubit is on a different substrate from the inductive element.

7. The structure of claim 1 , wherein the interconnect structure is a solder bump.

8. The structure of claim 1 , wherein the interconnect structure is a through-silicon via.

9. The structure of claim 1 , wherein the capacitive element comprises the interconnect structure.

10. The structure of claim 1 , wherein the inductive element and the capacitive element together form a readout resonator configured to readout the qubit.

11. The structure of claim 1 , wherein the interconnect structure is a through-silicon via.

12. The structure of claim 1 , wherein the inductive element and the capacitive element together form a readout resonator configured to readout the qubit.

13. A structure comprising:
an inductive element on a first surface;
a capacitive element on the first surface and a second surface such that the capacitive element is separate from the inductive element, wherein a qubit is on the second surface; and
an interconnect structure between the first surface and the second surface.

14. The structure of claim 13 , wherein the first surface and the second surface are opposite surfaces on a substrate.

15. The structure of claim 13 , wherein the first surface and the second surface are on different substrates.

16. The structure of claim 13 , wherein the qubit is on an opposite side of a substrate from the inductive element.

17. The structure of claim 13 , wherein the qubit is on a different substrate from the inductive element.

18. The structure of claim 13 , wherein the capacitive element comprises the interconnect structure.

19. A structure comprising:
an inductive element on a first surface;
a capacitive element on the first surface and a second surface such that the capacitive element is separate from the inductive element; and
an interconnect structure between the first surface and the second surface, wherein the interconnect structure is a solder bump.

Assignees

• IBM

Inventors

• Brink Markus
• Corcoles-Gonzalez Antonio D
• Gambetta Jay M
• Rosenblatt Sami
• Solgun Firat

Classifications

• H01P5/028

  between strip lines · CPC title

• H01P7/086

  Coplanar waveguide resonators (H01P7/088 takes precedence) · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L39/025 Primary

  Electricity · mapped topic

• H01L23/481

  Electricity · mapped topic