VCO selection and amplitude management using center tap inductor
US-10116260-B2 · Oct 30, 2018 · US
US2016359456A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016359456-A1 |
| Application number | US-201514733175-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 8, 2015 |
| Priority date | Jun 8, 2015 |
| Publication date | Dec 8, 2016 |
| Grant date | — |
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Aspects of this disclosure relate to a first die includes an LC resonant circuit including a first capacitive element, such as a capacitor or a varactor, and an inductive element. The LC resonant circuit is configured to generate a signal having a frequency of oscillation. The first die includes bump pads electrically coupled to both ends of the first capacitive element. A second die can be flip chip mounted on the first die. Bumps can electrically connect a second capacitive element of the second die in parallel with the first capacitive element of the first die. This can increase the Q factor of the LC resonant circuit.
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1 . A system comprising: a first die comprising: an LC resonant circuit comprising a first capacitive element and an inductive element, the first capacitive element having a first end and a second end; a second die stacked on the first die, the second die comprising a second capacitive element having a first end and a second end; a first bump electrically coupling the first end of the first capacitive element to the first end of the second capacitive element; and a second bump electrically coupling the second end of the first capacitive element to the second end of the second capacitive element, such that the first bump and the second bump electrically connect the first capacitive element in parallel with the second capacitive element, wherein the first capacitive element being in parallel with the second capacitive element causes a quality factor of a resonator that includes the LC resonant circuit to be increased. 2 . The system of claim 1 , wherein the first capacitive element comprises at least one of a first varactor diode or a first capacitor. 3 . The system of claim 1 , wherein the first bump comprises at least one of a copper pillar, a solder ball, or a solder joint. 4 . The system of claim 1 , wherein a second circuit on the second die is a flipped, mirror image of a first circuit on the first die, and wherein the first circuit comprises the first capacitive element. 5 . (canceled) 6 . The system of claim 1 , wherein the first circuit the comprises at least one capacitor and at least one varactor. 7 . The system of claim 1 , further comprising: a package encapsulating the first die and the second die; an insulator disposed between the first die and the second die; and a wire bond coupling the first die to a pin of the package. 8 . The system of claim 1 , wherein the inductive element is coupled to the first capacitive element by way of a microstrip line of the first die, and wherein the second die comprises a second microstrip line coupled in parallel with the first microstrip line by way of the first bump so as to lower a loss associated with the resonator. 9 . The system of claim 1 , wherein the first die comprises a voltage controlled oscillator (VCO), the VCO comprising the LC resonant circuit, wherein the VCO has a resonant frequency that is based on a tuning voltage received by the VCO. 10 . The system of claim 9 , further comprising a plurality of active circuits on the first die. 11 . A die comprising: an LC resonant circuit configured to generate a signal at an output node, the signal oscillating at a resonant frequency, the LC resonant circuit comprising: a capacitive element having a first end and a second end; an inductive element electrically coupled to the capacitive element; and an circuit element electrically coupled in series between the capacitive element and the output node, the circuit element effecting the resonant frequency of the signal; a first bump pad electrically coupled to the first end of the capacitive element; and a second bump pad electrically coupled to the second end of the capacitive element. 12 . The die of claim 11 , wherein the capacitive element comprises at least one of a varactor diode or a capacitor. 13 . The die of claim 11 , wherein the inductive element is configured as a choke inductor, and wherein the choke inductor is coupled to the capacitive element by way of a microstrip line. 14 . The die of claim 11 , wherein the LC resonant circuit comprises a second capacitive element, and wherein the die comprises a third bump pad connected to the second capacitive element. 15 . The die of claim 11 , wherein the die comprises a voltage controlled oscillator, wherein the voltage controlled oscillator comprises the LC resonant circuit. 16 . The die of claim 11 , wherein the first bump pad is disposed on a first microstrip and the second bump pad is disposed on a second microstrip. 17 . A method of manufacturing a monolithic microwave integrated circuit, the method comprising: electrically coupling a first bump from a first end of a first capacitive element on a first integrated circuit die to a first end of a second capacitive element on a second integrated circuit die, wherein the first capacitive element is included in an LC resonant circuit of the first integrated circuit die; and electrically coupling a second bump from a second end of the first capacitive element on the first die to a second end of the second capacitive element on the second integrated circuit die such that the second capacitive element is electrically connected in parallel with the first capacitive element. 18 . The method of claim 17 , wherein the first bump comprises at least one of a copper pillar, a solder ball, or a solder joint. 19 . The method of claim 17 , further comprising mounting the second die on the first integrated circuit die such that bump pads of the first integrated circuit die are aligned with corresponding bump pads of the second integrated circuit die. 20 . The method of claim 17 , further comprising filling a space between the first integrated circuit die and the second die with an insulating material; and encasing the first die and the second integrated circuit die in a packaging material. 21 . The system of claim 1 , wherein at least a part of the second capacitive element is vertically positioned above the first capacitive element, and wherein a footprint of the second die in within a footprint of the first die.
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