Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer

Patent metadata

Field	Value
Publication number	US-10622233-B2
Application number	US-201816054725-A
Country	US
Kind code	B2
Filing date	Aug 3, 2018
Priority date	Sep 5, 2016
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

Disclosed herein is a technology related to the amelioration (e.g., correction) of global wafer distortion based on a determination of localized distortions of a semiconductor wafer. Herein, a distortion is either an out-of-plane distortion (OPD) or in-plane distortion (IPD). The reference plane for this distortion is based on the plane shared by the surface of a presumptively flat semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1. A method comprising:
obtaining shape data of a semiconductor wafer, wherein the shape data represents a global distortion of the semiconductor wafer;
determining, based on the obtained shape data, local distortion of each of multiple discretized pixels of the semiconductor wafer;
estimating one or more forces at each pixel that produces the determined local distortion of each of the multiple pixels and contributes to the global distortion of the semiconductor wafer;
for each of the multiple discretized pixels and using the estimated forces for each pixel, generating an amelioration pattern of a backside layer that, when applied to a corresponding discretized pixel of a backside of the semiconductor wafer, ameliorates the global distortion of the semiconductor wafer.

2. A method of claim 1 , further comprising applying the backside layer to the backside of the semiconductor wafer, wherein the backside layer is patterned in accordance with the generated amelioration pattern.

3. A method of claim 1 , wherein the generation of the amelioration pattern includes:
storing the amelioration pattern;
storing an image of the amelioration pattern; or
producing instructions to direct a tool to apply the backside layer to the backside of the semiconductor wafer using the generated amelioration pattern; or
determining dimensions of the amelioration pattern for the backside layer applied to the semiconductor wafer; or
determining dimensions and/or composition of the backside layer to be applied to the backside of the substrate.

4. A method of claim 1 , wherein the global distortion includes a distortion of a wafer that manifests across a substantial portion of the wafer.

5. A method of claim 1 , wherein the local distortion includes a distortion that manifests over an insubstantial portion of the wafer.

6. A method of claim 1 , wherein the global distortion and/or local distortion includes out-of-plane distortion and/or in-plane distortion.

7. A method of claim 1 , further comprising:
determining an impact of the amelioration pattern on an overlay error of one or more patterns on a front side of the semiconductor wafer, the front side of being on the opposite the backside of the semiconductor wafer; and
feed-forwarding the impact of the amelioration pattern to other tools being used in a fabrication process of the wafer.

8. A method of claim 1 , wherein the determining of local distortions includes:
mapping the multiple discretized pixels onto the semiconductor wafer, wherein each multiple discretized pixel being mapped to an area of the semiconductor wafer;
for each of the multiple discretized pixels, calculating a value of local distortion that represents amplitude of distortion for that pixel.

9. A method of claim 1 , wherein the estimating the one or more forces at each pixel includes:
modeling forces on a pixel that replicates the local distortion of that pixel and contributes to the global distortion;
iteratively performing the modeling with varying forces until an optimized value of one or more forces is found for each pixel;
assigning the optimized value of the one or more forces to its pixel.

10. A method of claim 1 , wherein the generation of the amelioration pattern includes:
obtaining a range of distortion that is possible for each pixel;
limiting the amelioration pattern to account for distortions within the obtained range.

11. A method of claim 1 , wherein, when the generated amelioration pattern is applied to the corresponding discretized pixel of a backside of the semiconductor, the amelioration pattern ameliorates the local distortion of the semiconductor wafer.

12. A system of claim 11 further comprising a backside-pattern component to apply the backside layer to the backside of the semiconductor wafer, wherein the backside layer is patterned in accordance with the generated amelioration pattern.

13. A system of claim 11 , wherein the generation of the backside-pattern generator includes:
storage of the amelioration pattern;
storage of an image of the amelioration pattern; or
production of instructions to direct a tool to apply the backside layer to the backside of the semiconductor wafer using the generated amelioration pattern; or
determination of dimensions of the amelioration pattern for the backside layer applied to the semiconductor wafer; or
determination of dimensions and/or composition of the backside layer to be applied to the backside of the substrate.

14. A system of claim 11 , wherein the determination of local distortions includes:
generation of a map of the multiple discretized pixels onto the semiconductor wafer, wherein each multiple discretized pixel being mapped to an area of the semiconductor wafer;
calculation, for each of the multiple discretized pixels, of a value of local distortion that represents amplitude of distortion for that pixel.

15. A method comprising:
obtaining shape data of a semiconductor wafer, wherein the shape data represents a distortion of the semiconductor wafer;
calculating equibiaxial wafer stress of the semiconductor wafer, wherein the calculations are based on the obtained shape data;
obtaining initial custom parameters of the semiconductor wafer;
calculating wafer distortion based on the calculated equibiaxial wafer stress and the obtained, at least in part on custom parameters;
determining the residual wafer shape as a difference between the obtained wafer shape data and a calculated wafer shape;
updating custom parameters to reduce residual wafer shape or wafer distortion, or both;
optimizing a solution to plate theory equations by repeating the wafer-shape calculation and residual wafer shape determination with differing custom parameters;
generating an amelioration pattern based, at least in part, on the solution, the amelioration pattern being capable ameliorating the distortion of the semiconductor wafer when applied to a backside of the semiconductor wafer, ameliorates the distortion of the semiconductor wafer.

16. A method of claim 15 , wherein the optimizing of the solution is based, at least in part, on one or more metrics of the semiconductor wafer falling within a predefined range.

17. A method of claim 1 , wherein the generation of the amelioration pattern includes: producing a coverage layout based on the generated amelioration pattern, wherein each pixel of a coverage layout is based digital patterns in a coverage library.

18. A non-transitory computer-readable storage medium comprising instructions that when executed cause a processor of a computing device to perform the method of claim 1 .

19. A system comprising:
a wafer-shape meter to obtain shape data of a semiconductor wafer, wherein the shape data represents a global distortion of the semiconductor wafer;
a wafer simulator to determine, based, at least in part, on the obtained shape data, local distortion of each of multiple discretized pixels of the semiconductor wafer;
a stress estimator to estimate one or more forces at each pixel that produces the determined local distortion of each of the multiple pixels and contributes to the global distortion of the semiconductor wafer;
a backside-pattern generator to generate, for each of the multiple discretized pixels and using the estimated forces for each pixel, an amelioration pattern of a backside layer that, when applied to a corresponding discretized pixel of a backside of the semiconductor wafer, ameliorates the global distortion of the semiconductor wafer.

20. A method

Assignees

• Tokyo Electron Ltd

Inventors

• Hooge Joshua
• Ip Nathan
• Estrella Joel
• Devilliers Anton

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title