Semiconductor device

Patent metadata

Field	Value
Publication number	US-10607997-B2
Application number	US-201916543216-A
Country	US
Kind code	B2
Filing date	Aug 16, 2019
Priority date	Dec 19, 2016
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a plurality of lower electrodes on the substrate, individual lower electrodes of the plurality of lower electrodes being repeatedly arranged in a first direction and in a second direction that crosses the first direction; and
a first electrode support contacting a sidewall of at least one of the plurality of lower electrodes to support the at least one of the plurality of lower electrodes, the first electrode support including:
a first support region, the first support region including first openings, and
a second support region at a border of the first support region, the second support region including first sidewalls extending in the first direction, second sidewalls extending in the second direction, and connecting sidewalls connecting the first sidewalls with the second sidewalls, the connecting sidewalls having a linear shape in a top view.

2. The semiconductor device as claimed in claim 1 , wherein at least a portion of an outer perimeter of the first electrode support includes a zigzag pattern.

3. The semiconductor device as claimed in claim 1 , wherein only the first support region among the first and second support regions includes the first openings.

4. The semiconductor device as claimed in claim 3 , wherein each of the first openings is shared by three electrodes of the plurality of lower electrodes.

5. The semiconductor device as claimed in claim 3 , wherein:
the first support region contacts sidewalls of first lower electrodes of the plurality of lower electrodes, the first openings extending through the first support region to at least partially expose the first lower electrodes, and
the second support region contacts sidewalls of second lower electrodes of the plurality of lower electrodes, the second support region including no openings between adjacent second lower electrodes of the plurality of lower electrodes.

6. The semiconductor device as claimed in claim 5 , wherein a distance between an outermost row of the second lower electrodes to an outer perimeter of the first electrode support is equal to or smaller than a distance between two adjacent second lower electrodes within a same row.

7. The semiconductor device as claimed in claim 5 , wherein the second support region includes at least two rows of second lower electrodes between the first support region and an outer perimeter of the first electrode support.

8. The semiconductor device as claimed in claim 1 , wherein the first electrode support includes silicon nitride.

9. The semiconductor device as claimed in claim 1 , further comprising a second electrode support, the second electrode support contacting a sidewall of the at least one of the plurality of lower electrodes, and the first and second electrode supports being spaced apart from each other along a direction normal to the substrate to overlap each other.

10. The semiconductor device as claimed in claim 9 , wherein the second electrode support includes second openings, the second openings being aligned with and overlapping the first openings in the first electrodes support.

11. The semiconductor device as claimed in claim 10 , wherein each pair of aligned first and second openings is shared by three electrodes of the plurality of lower electrodes.

12. The semiconductor device as claimed in claim 1 , wherein the plurality of lower electrodes are arranged in rows on the substrate, the rows extending in the first direction and being spaced apart from each other in the second direction, and every two rows adjacent to each other in the second direction being offset with respect to each other in the first direction to have lower electrodes in the rows aligned along a third direction at an oblique angle with respect to the first and second directions.

13. The semiconductor device as claimed in claim 12 , wherein the third direction extends in parallel to first and third connecting sidewalls of the connecting sidewalls.

14. The semiconductor device as claimed in claim 13 , wherein:
the rows of the plurality of lower electrodes offset with respect to each other in the first direction further have lower electrodes in the rows aligned along a fourth direction, the third and fourth directions being symmetrical with respect to each other relative to the second direction, and
the fourth direction extends in parallel to second and fourth connecting sidewalls of the connecting sidewalls.

15. The semiconductor device as claimed in claim 1 , wherein an entirety of each of the connecting sidewalls between corresponding first and second sidewalls is linear in the top view.

16. A semiconductor device, comprising:
a substrate;
a plurality of lower electrodes arranged in rows on the substrate, the rows extending in a first direction and being spaced apart from each other in a second direction that crosses the first direction, every two rows adjacent to each in the second direction being offset with respect to each other in the first direction to have lower electrodes aligned along a third direction at an oblique angle with respect to the first and second directions;
a first electrode support contacting a sidewall of at least one of the plurality of lower electrodes to support the at least one of the plurality of lower electrodes, the first electrode support including:
a first support region, the first support region including first openings, and
a second support region at a border of the first support region, the second support region including first sidewalls extending in the first direction, second sidewalls extending in the second direction, and connecting sidewalls connecting the first sidewalls with the second sidewalls, at least some of the connecting sidewalls being parallel to the third direction.

17. The semiconductor device as claimed in claim 16 , wherein each of the connecting sidewalls has a linear shape in a top view.

18. The semiconductor device as claimed in claim 16 , wherein:
the first support region includes first electrodes of the plurality of lower electrodes, each of the first openings in the first support region being shared by three first electrodes of the plurality of lower electrodes, and
the second support region includes second electrodes of the plurality of lower electrodes, the second support region including no openings between adjacent second electrodes of the plurality of lower electrodes.

19. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a plurality of peripheral lower electrodes in the peripheral region of the substrate, individual lower electrodes of the plurality of peripheral lower electrodes being repeatedly arranged in a first direction and in a second direction that crosses the first direction;
a peripheral dielectric film along profiles of the plurality of peripheral lower electrodes;
a plurality of peripheral upper electrodes on the peripheral dielectric film, the pluralities of peripheral upper and lower electrodes with the peripheral dielectric film therebetween defining peripheral capacitors in the peripheral region;
a plurality of cell lower electrodes in the cell region of the substrate, individual lower electrodes of the plurality of cell lower electrodes being repeatedly arranged in the first and second directions;
a cell dielectric film along profiles of the plurality of cell lower electrodes;
a plurality of cell upper electrodes on the cell dielectric film, the pluralities of cell upper and lower electrodes with the cell dielectric

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ye Ram
• Lee Won Chul

Classifications

• H01L28/87

  Electricity · mapped topic

• H01L27/10852 Primary

  Electricity · mapped topic

• H01L28/91

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H01L28/56

  Electricity · mapped topic