Capacitor structure and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-2016365409-A1
Application number	US-201615159809-A
Country	US
Kind code	A1
Filing date	May 20, 2016
Priority date	Jun 15, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

First claim

What is claimed is:

1 . A capacitor structure, comprising:
a plurality of bottom electrodes horizontally spaced apart from each other; a support structure covering sidewalls of the bottom electrodes; a top electrode surrounding the support structure and the bottom electrodes; and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes, wherein an uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

2 . The capacitor structure of claim 1 , wherein the support structure includes an upper support pattern and a lower support pattern vertically spaced apart from each other,
the upper support pattern is in contact with an upper portion of a sidewall of each of the bottom electrodes, and the lower support pattern is in contact with a lower portion of the sidewall of each of the bottom electrodes.

3 . The capacitor structure of claim 2 , wherein an upper surface of the upper support pattern is positioned at a higher level than the uppermost surface of each of the bottom electrodes.

4 . The capacitor structure of claim 3 , wherein the upper support pattern has a sidewall exposed above the uppermost surface of each of the bottom electrodes.

5 . The capacitor structure of claim 4 , wherein the uppermost surface of each of the bottom electrodes contacts the dielectric layer.

6 . The capacitor structure of claim 4 , wherein the top electrode covers the upper surface of the upper support pattern and each exposed sidewall, and extends on the uppermost surface of each of the bottom electrodes.

7 . The capacitor structure of claim 6 , wherein the top electrode is provided between the upper support pattern and the lower support pattern, and under the lower support pattern to cover the sidewalls of the bottom electrodes.

8 . The capacitor structure of claim 2 , wherein each of the bottom electrodes penetrates the lower support pattern.

9 . The capacitor structure of claim 8 , wherein a lower surface of the lower support pattern is positioned at a higher level than a lowest surface of each of the bottom electrodes.

10 . The capacitor structure of claim 2 , wherein at least a portion of the top electrode penetrates the upper support pattern and the lower support pattern to cover the sidewalls of the bottom electrodes.

11 . The capacitor structure of claim 10 , wherein the upper and lower support patterns include a plurality of upper and lower openings, respectively,
the at least a portion of the top electrode penetrates the upper supper pattern through the plurality of upper openings, the at least a portion of the top electrode penetrates the lower supper pattern through the plurality of lower openings, and each of the plurality of upper and lower openings have an outer boundary exposing the bottom electrodes.

12 . The capacitor structure of claim 11 , wherein, when viewed in a plan view, the plurality of upper openings and the plurality of lower openings overlap each other.

13 . The capacitor structure of claim 1 , wherein the bottom electrodes are inserted in the top electrode, and the support structure is provided in the top electrode to contact the sidewalls of the bottom electrodes.

14 . A semiconductor device, comprising:
a plurality of transistors on a substrate; and a capacitor structure connected to the transistors, and including: a top electrode on the substrate; a plurality of bottom electrodes inserted in the top electrode and connected to a corresponding transistor among the plurality of transistors; a support structure provided in the top electrode and covering a portion of sidewalls of the bottom electrodes; and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes, wherein an uppermost surface of the support structure is positioned at higher level than an uppermost surface of each of the bottom electrodes.

15 . The semiconductor device of claim 14 , wherein the support structure includes:
an upper support pattern on the substrate; and a lower support pattern provided between the substrate and the upper support pattern and spaced apart from the upper support pattern, and wherein the upper support pattern is in contact with an upper portion of a sidewall of each of the bottom electrodes, and the lower support pattern is in contact with a lower portion of the sidewall of each of the bottom electrodes.

16 . The semiconductor device of claim 15 , wherein an upper surface of the upper support pattern is positioned at a higher level than the uppermost surface of each of the bottom electrodes.

17 . The semiconductor device of claim 16 , wherein the upper support pattern has a sidewall exposed above the uppermost surface of each of the bottom electrodes.

18 . The semiconductor device of claim 17 , wherein the top electrode covers the upper surface of the upper support pattern and the exposed sidewall, and extends on the uppermost surface of each of the bottom electrodes.

19 . A capacitor structure, comprising:
a plurality of bottom electrodes horizontally spaced apart from each other; a support structure covering sidewalls of the bottom electrodes; a top electrode surrounding the support structure and the bottom electrodes; and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes, wherein the support structure includes an upper support pattern and a lower support pattern vertically spaced apart from each other, an upper surface of the upper support pattern is positioned at a higher level than the uppermost surface of each of the bottom electrodes.

20 . The semiconductor device of claim 19 , wherein the upper support pattern has a thickness greater than that of the lower support pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Min
• Kim Hyongsoo
• Jun Jongryul

Classifications

• H10D1/716 Primary

  having vertical extensions · CPC title

• H01L28/91

  Electricity · mapped topic

• H01L28/87

  Electricity · mapped topic

• H01L28/60

  Electricity · mapped topic

• H01L28/90

  Electricity · mapped topic