Semiconductor device

Patent metadata

Field	Value
Publication number	US-10032778-B2
Application number	US-201715668847-A
Country	US
Kind code	B2
Filing date	Aug 4, 2017
Priority date	Dec 19, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a plurality of lower electrodes disposed on the substrate, wherein individual lower electrodes of the plurality of lower electrodes are repeatedly arranged in a first direction and in a second direction that crosses the first direction; and
a first electrode support contacting a sidewall of at least one of the lower electrodes to support the at least one of the lower electrodes,
wherein the first electrode support comprises a first support region and a second support region disposed at a border of the first support region, wherein the first support region includes a first opening,
wherein an outer sidewall of the first electrode support comprises a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first sidewall with the second sidewall,
wherein the second support region comprises the connecting sidewall, and
wherein, in a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

2. The semiconductor device of claim 1 , wherein at least one of the lower electrodes is in contact with the second support region.

3. The semiconductor device of claim 2 , wherein the lower electrodes include a row of lower electrodes arranged in the first direction, and
wherein a first lower electrode and a second lower electrode of the row of lower electrodes, which are respectively disposed at opposite ends of the row of lower electrodes, are in contact with the second support region.

4. The semiconductor device of claim 1 , further comprising a second electrode support disposed between the substrate and the first electrode support,
wherein the second electrode support is in contact with the sidewall of the at least one of the lower electrodes to support the at least one of the lower electrodes, wherein an outer sidewall of the second electrode support has a shape corresponding to a shape of the outer sidewall of the first electrode support.

5. The semiconductor device of claim 4 , wherein the second electrode support comprises a third support region and a fourth support region disposed at a border of the third support region, wherein the third support region includes a second opening.

6. The semiconductor device of claim 1 , wherein a first boundary of an upper surface of the first electrode support, corresponding to the connecting sidewall, extends in a third direction, wherein the third direction crosses the first and second directions.

7. The semiconductor device of claim 6 , wherein a pair of neighboring lower electrodes of the lower electrodes are spaced apart from each other by a first distance,
wherein the first boundary of the upper surface of the first electrode support is spaced apart from a lower electrode of the lower electrodes, disposed most adjacent to the first boundary of the upper surface of the first electrode support, by a second distance, and
wherein the first distance and the second distance are substantially equal to each other.

8. The semiconductor device of claim 1 , wherein the connecting sidewall overlaps the lower electrodes in at least one of the first direction or the second direction.

9. The semiconductor device of claim 1 , wherein a first boundary of an upper surface of the first electrode support, corresponding to the connecting sidewall, has a zigzag shape.

10. The semiconductor device of claim 1 , wherein a first boundary of an upper surface of the first electrode support, corresponding to the connecting sidewall, has a wavy shape.

11. The semiconductor device of claim 1 , wherein the first support region further includes a plurality of first openings,
wherein a first lower electrode of the lower electrodes, which is in contact with the first support region, is exposed by no more than one first opening of the first openings.

12. The semiconductor device of claim 1 , wherein an uppermost surface of the lower electrodes is flush with an upper surface of the first electrode support.

13. The semiconductor device of claim 1 , wherein at least one of the lower electrodes protrudes higher than an upper surface of the first electrode support, with respect to a first surface of the substrate.

14. The semiconductor device of claim 1 , wherein the lower electrodes comprise a first row of lower electrodes, a second row of lower electrodes and a third row of lower electrodes consecutively arranged,
wherein each of the first, second and third rows of lower electrodes extends in the first direction, and wherein the first and second directions are perpendicular to each other,
wherein a first line that extends in the first direction passes through each lower electrode of the second row of lower electrodes, and
wherein a second line that extends in the second direction passes through one of the lower electrodes of the first row of electrodes, through one of the lower electrodes of the third row of electrodes, but not through one of the lower electrodes of the second row of electrodes.

15. The semiconductor device of claim 1 , wherein the at least one of the lower electrodes comprises the sidewall and a bottom surface connected to the sidewall,
wherein the sidewall of the at least one of the lower electrodes extends in a thickness direction of the first electrode support, and the bottom surface of the at least one of the lower electrodes is substantially parallel with an upper surface of the substrate,
wherein the thickness direction of the first electrode support crosses a plane on which the upper surface of the substrate extends.

16. The semiconductor device of claim 1 , wherein the lower electrodes have a pillar shape extending in a thickness direction of the first electrode support.

17. The semiconductor device of claim 1 , further comprising:
a capacitor insulating film, wherein the capacitor insulating film extends along a profile of the lower electrodes, along an upper surface of the first electrode support and along a lower surface of the first electrode support; and
an upper electrode on the capacitor insulating film.

18. A semiconductor device, comprising:
a substrate comprising a cell region and a peripheral region;
a plurality of first lower electrodes disposed on the cell region, wherein individual first lower electrodes of the plurality of first lower electrodes are repeatedly arranged in a first direction and in a second direction that crosses the first direction;
a plurality of second lower electrodes disposed on the peripheral region, wherein individual second lower electrodes of the plurality of second lower electrodes are repeatedly arranged in the first direction and in the second direction;
a first electrode support in contact with a sidewall of at least one of the first lower electrodes to support the at least one of the first lower electrodes; and
a second electrode support in contact with a sidewall of at least one of the second lower electrodes to support the at least one of the second lower electrodes,
wherein an outer sidewall of the first electrode support comprises a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a first connecting sidewall connecting the first sidewall with the second sidewall, and
a boundary of an upper surface of the first electrode support, corresponding to the first connecting sidewall, extends in a third direction, wherein the third direction crosses the fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ye Ram
• Lee Won Chul

Classifications

• H01L28/56

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H01L28/91

  Electricity · mapped topic

• H01L28/87

  Electricity · mapped topic

• H01L27/10852 Primary

  Electricity · mapped topic