Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-9870827-B2
Application number	US-201615359017-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Nov 26, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first circuit including first memory blocks, a first reference memory block, a third circuit, a fourth circuit, a fifth circuit, a sixth circuit, and a seventh circuit; and
a second circuit including operation blocks, a second reference memory block, an eighth circuit, a ninth circuit, and a tenth circuit,
wherein the first memory blocks are arranged in a matrix,
wherein the first memory blocks and the first reference memory block each include a first memory cell,
wherein the first memory blocks are configured to store first data,
wherein the third circuit is configured to select the first memory cell to which the first data is written,
wherein the fourth circuit is configured to supply the first data,
wherein the fifth circuit is configured to supply a potential corresponding to a coefficient used for operation to the first memory blocks and the first reference memory block,
wherein the sixth circuit is configured to bring the first reference memory block and the seventh circuit into conduction and to bring a selected first memory block and the seventh circuit into conduction,
wherein the seventh circuit is configured to output second data obtained by operation using a signal output from the first reference memory block and a signal output from the selected first memory block to the second circuit,
wherein the operation blocks are provided in a row direction,
wherein each of the operation blocks includes a second memory block and a third memory block,
wherein the second memory block, the third memory block, and the second reference memory block each include a second memory cell,
wherein the second memory block and the third memory block are each configured to store the second data,
wherein the eighth circuit is configured to select the second memory cell to which the second data is written,
wherein the ninth circuit is configured to supply a potential corresponding to a coefficient used for operation to the second memory block or the third memory block and the second reference memory block,
wherein the tenth circuit is configured to output third data obtained by operation using a signal output from the second reference memory block and a signal output from a selected second memory block or the third memory block,
wherein the second data is alternately input to the second memory block and the third memory block, and
wherein one of the second memory block and the third memory block is configured to perform operation while the second data is input to the other of the second memory block and the third memory block.

2. The semiconductor device according to claim 1 ,
wherein the first memory blocks include first transistors,
wherein one of the first transistors is provided in each column,
wherein the first reference memory block includes a second transistor,
wherein the first memory cell includes a third transistor, a fourth transistor, and a first capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and one electrode of the first capacitor,
wherein the other of the source and the drain of the third transistor is electrically connected to the fourth circuit,
wherein a gate of the third transistor is electrically connected to the third circuit,
wherein the other electrode of the first capacitor is electrically connected to the fifth circuit,
wherein one of a source and a drain of the fourth transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of a first transistor provided in the same column,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a gate of one of the first transistors and a gate of the second transistor are electrically connected to the sixth circuit, and
wherein the other of the source and the drain of one of the first transistors and the other of the source and the drain of the second transistor are electrically connected to the seventh circuit.

3. The semiconductor device according to claim 1 ,
wherein second memory cells included in the second memory block, the third memory block, and the second reference memory block each include a fifth transistor, a sixth transistor, and a second capacitor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the sixth transistor and one electrode of the second capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the seventh circuit,
wherein the other electrode of the second capacitor is electrically connected to the ninth circuit, and
wherein one of a source and a drain of the sixth transistor is electrically connected to a power supply line.

4. The semiconductor device according to claim 3 ,
wherein the second memory block and the third memory block each include a seventh transistor, an eighth transistor, and a first inverter circuit,
wherein one seventh transistor and one eighth transistor are provided in each row,
wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor provided in the same row,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor provided in the same row,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the eighth circuit,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the tenth circuit,
wherein a gate of the eighth transistor is electrically connected to an output terminal of the first inverter circuit, and
wherein a gate of the seventh transistor is electrically connected to an input terminal of the first inverter circuit.

5. The semiconductor device according to claim 4 ,
wherein an input terminal of a second inverter circuit is electrically connected to the gate of the seventh transistor included in the second memory block, and
wherein an output terminal of the second inverter circuit is electrically connected to the gate of the seventh transistor included in the third memory block.

6. The semiconductor device according to claim 3 , wherein the other of the source and the drain of the fifth transistor is electrically connected to the fourth circuit, the gate of the fifth transistor is electrically connected to the third circuit, and the other of the source and the drain of the sixth transistor is electrically connected to the tenth circuit.

7. The semiconductor device according to claim 1 , wherein transistors included in the first memory cell and the second memory cell each include an oxide semiconductor in a region where a channel is formed.

8. The semiconductor device according to claim 7 , wherein the oxide semiconductor includes In, Zn, and M, where M is Al, Ga, Y, or Sn.

9. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a display device.

10. A semiconductor device comprising:
a first circuit including first memory blocks, a first reference memory block, a third circuit, a fourth circuit, a fifth circuit, a sixth circuit, and a seventh circuit; and
a second circuit including operation blocks, a second reference memory block, an eighth circuit, a ninth circuit, and a tenth circuit,
wherein the first memory blocks are arranged in a matrix and includes a first transistor,
wherein the fi

Assignees

• Semiconductor Energy Lab

Inventors

• Nakagawa Takashi
• Inoue Hiroki
• Akasawa Fumika
• Kurokawa Yoshiyuki

Classifications

• H01L27/14616

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• H01L27/124

  Electricity · mapped topic

• H01L27/14643

  Electricity · mapped topic