Magnetic domain wall shift register memory devices with high magnetoresistance ratio structures

Patent metadata

Field	Value
Publication number	US-10580971-B2
Application number	US-201815892979-A
Country	US
Kind code	B2
Filing date	Feb 9, 2018
Priority date	Oct 6, 2014
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A method includes depositing a magnetic track layer on a seed layer, depositing an alloy layer on the magnetic track layer, depositing a tunnel barrier layer on the alloy layer, depositing a pinning layer on the tunnel barrier layer, depositing a synthetic antiferromagnetic layer spacer on the pinning layer, depositing a pinned layer on the synthetic antiferromagnetic spacer layer and depositing an antiferromagnetic layer on the pinned layer, and another method includes depositing an antiferromagnetic layer on a seed layer, depositing a pinned layer on the antiferromagnetic layer, depositing a synthetic antiferromagnetic layer spacer on the pinned layer, depositing a pinning layer on the synthetic antiferromagnetic layer spacer, depositing a tunnel barrier layer on the pinning layer, depositing an alloy layer on the tunnel barrier layer and depositing a magnetic track layer on alloy layer.

First claim

What is claimed is:

1. A method of fabricating a magnetic domain wall shift register memory device, the method comprising:
depositing a magnetic track layer on a substrate;
depositing a pinning layer on the magnetic track layer, the pinning layer comprising CoFeB;
depositing a synthetic antiferromagnetic (SAF) layer spacer on the pinning layer;
depositing a pinned layer on the SAF spacer layer; and
depositing an antiferromagnetic layer on the pinned layer.

2. The method as claimed in claim 1 , wherein a seed layer is arranged on the substrate beneath the magnetic track layer.

3. The method as claimed in claim 2 , wherein the seed layer comprises a template layer and a metallic layer disposed on the template layer.

4. The method as claimed in claim 1 , wherein the magnetic track layer is a magnetic alloy.

5. The method as claimed in claim 1 , wherein the pinning layer comprises a Fe content of about 10% to 90%.

6. The method as claimed in claim 1 , wherein the SAF spacer layer comprises Ru.

7. The method as claimed in claim 1 , wherein the pinned layer is CoFe.

8. The method as claimed in claim 1 , wherein the pinned layer is CoFeB.

9. The method as claimed in claim 1 , wherein the antiferromagnetic layer is PtMn.

10. The method as claimed in claim 1 , wherein the antiferromagnetic layer is IrMn.

11. A method for fabricating a magnetic domain wall shift register memory device, the method comprising:
depositing a magnetic track layer on a substrate;
depositing a pinning layer directly on the magnetic track layer, the pinning layer comprising CoFeB;
depositing a synthetic antiferromagnetic (SAF) spacer layer on the pinning layer;
depositing a pinned layer on the SAF layer spacer layer; and
depositing an antiferromagnetic layer on the pinned layer.

12. The method as claimed in claim 11 , wherein a seed layer is arranged on the substrate beneath the magnetic track layer, and the seed layer comprises a template layer and a metallic layer disposed on the template layer.

13. The method as claimed in claim 11 , wherein the antiferromagnetic layer is PtMn.

14. The method as claimed in claim 11 , wherein the antiferromagnetic layer is IrMn.

15. The method as claimed in claim 11 , wherein the pinned layer is CoFe.

16. The method as claimed in claim 11 , wherein the pinned layer is CoFeB.

17. The method as claimed in claim 11 , wherein the SAF spacer layer is Ru.

18. The method as claimed in claim 11 , wherein the pinning layer is CoFeB.

19. The method as claimed in claim 11 , wherein the magnetic track layer is a magnetic alloy.

20. The method as claimed in claim 18 , wherein the pinning layer comprises a Fe content of about 10% to about 90%.

Assignees

• IBM
• Ind Tech Res Inst
• Industrial Tech Research

Inventors

• Hu Guohan
• Chien Cheng-Wei

Classifications

• G11B5/33

  Structure or manufacture of flux-sensitive heads, {i.e. for reproduction only; Combination of such heads with means for recording or erasing only}({Single head using magnetic domains for scanning G11B5/4946; multiple head for scanning G11B5/4907 and subgroups } ; general details therefor G11B5/133 - G11B5/255) · CPC title

• G11C19/0808 Primary

  using magnetic domain propagation · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C19/0841

  using electric current · CPC title

• H01L43/02

  Electricity · mapped topic