Magnetic domain wall shift register memory devices with high magnetoresistance ratio structures

Patent metadata

Field	Value
Publication number	US-9431600-B2
Application number	US-201414506798-A
Country	US
Kind code	B2
Filing date	Oct 6, 2014
Priority date	Oct 6, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A device includes a seed layer, a magnetic track layer disposed on the seed layer, an alloy layer disposed on the magnetic track layer, a tunnel barrier layer disposed on the alloy layer, a pinning layer disposed on the tunnel barrier layer, a synthetic antiferromagnetic layer spacer disposed on the pinning layer, a pinned layer disposed on the synthetic antiferromagnetic spacer layer and an antiferromagnetic layer disposed on the pinned layer, and another device includes a seed layer, an antiferromagnetic layer disposed on the seed layer, a pinned layer disposed on the antiferromagnetic layer, a synthetic antiferromagnetic layer spacer disposed on the pinned layer, a pinning layer disposed on the synthetic antiferromagnetic layer spacer, a tunnel barrier layer disposed on the pinning layer, an alloy layer disposed on the tunnel barrier layer and a magnetic track layer disposed on alloy layer.

First claim

What is claimed is:

1. A magnetic domain wall shift register memory device, comprising:
a seed layer;
a magnetic track layer disposed on the seed layer;
an alloy layer disposed on the magnetic track layer;
a tunnel barrier layer disposed on the alloy layer;
a pinning layer disposed on the tunnel barrier layer;
a synthetic antiferromagnetic (SAF) layer spacer disposed on the pinning layer;
a pinned layer disposed on the SAF spacer layer; and
an antiferromagnetic layer disposed on the pinned layer.

2. The device as claimed in claim 1 wherein the seed layer comprises:
a template layer; and
a metallic layer disposed on the template layer.

3. The device as claimed in claim 1 wherein the magnetic track layer is a magnetic alloy.

4. The device as claimed in claim 1 wherein the alloy layer is a CoFeB alloy and the tunnel barrier layer is MgO.

5. The device as claimed in claim 1 wherein the pinning layer is CoFeB layer, including a Fe content of about 10% to 90%.

6. The device as claimed in claim 1 wherein the pinned layer is selected from the group consisting of: CoFe and CoFeB.

7. The device as claimed in claim 1 further comprising a spacer layer disposed between the magnetic track layer and the alloy layer.

8. The device as claimed in claim 1 wherein the pinning layer, the SAF layer spacer, the pinned layer, and the antiferromagnetic layer are included in magnetic tunnel junction disposed on the tunnel barrier layer.

9. The device as claimed in claim 1 wherein the seed layer comprises:
a template layer; and
a metallic layer disposed on the template layer.

10. A magnetic domain wall shift register memory device, comprising:
a seed layer;
an antiferromagnetic layer disposed on the seed layer;
a pinned layer disposed on the antiferromagnetic layer;
a synthetic antiferromagnetic (SAF) layer spacer disposed on the pinned layer;
a pinning layer disposed on the SAF layer spacer;
a tunnel barrier layer disposed on the pinning layer;
an alloy layer disposed on the tunnel barrier layer; and
a magnetic track layer disposed on alloy layer.

11. The device as claimed in claim 10 wherein the antiferromagnetic layer is selected from the group consisting of PtMn and IrMn.

12. The device as claimed in claim 10 wherein the pinned layer is selected from the group consisting of: CoFe and CoFeB.

13. The device as claimed in claim 10 wherein the SAF spacer layer is Ru.

14. The device as claimed in claim 10 wherein the pinning layer is CoFeB layer, including a Fe content of about 10% to 90%.

15. The device as claimed in claim 10 wherein the alloy layer is a CoFeB alloy and the tunnel barrier layer is MgO.

16. The device as claimed in claim 10 wherein the magnetic track layer is a magnetic alloy.

17. The device as claimed in claim 10 further comprising a spacer layer disposed between the magnetic track layer and the alloy layer.

18. The device as claimed in claim 10 wherein the seed layer, the antiferromagnetic layer, pinned layer, the SAF layer spacer, and the pinning layer are included in magnetic tunnel junction disposed on the tunnel barrier layer.

19. A magnetic domain wall shift register memory device, comprising:
a seed layer;
a magnetic track layer disposed on the seed layer;
an alloy layer disposed on the magnetic track layer;
a tunnel barrier layer disposed on the alloy layer;
a pinning layer disposed on the tunnel barrier layer;
a synthetic antiferromagnetic (SAF) layer spacer disposed on the pinning layer and comprising Ru;
a pinned layer disposed on the SAF spacer layer; and
an antiferromagnetic layer disposed on the pinned layer and being selected from the group consisting of PtMn and IrMn.

Assignees

• IBM
• Ind Tech Res Inst

Inventors

• Hu Guohan
• Chien Cheng-Wei

Classifications

• G11C19/0841

  using electric current · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11B5/33

  Structure or manufacture of flux-sensitive heads, {i.e. for reproduction only; Combination of such heads with means for recording or erasing only}({Single head using magnetic domains for scanning G11B5/4946; multiple head for scanning G11B5/4907 and subgroups } ; general details therefor G11B5/133 - G11B5/255) · CPC title

• G11C19/0808 Primary

  using magnetic domain propagation · CPC title

• H01L43/02

  Electricity · mapped topic