Semiconductor device and wafer level package including such semiconductor device

Patent metadata

Field	Value
Publication number	US-2016276277-A1
Application number	US-201615006082-A
Country	US
Kind code	A1
Filing date	Jan 25, 2016
Priority date	Mar 20, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

First claim

1 . A semiconductor device, comprising:
an integrated circuit (IC) die having an active surface, wherein at least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface; a passivation layer on the active surface and covering the first on-chip metal pad and the second on-chip metal pad; and a redistribution layer (RDL) structure on the passivation layer, the RDL structure comprising:
a first landing pad disposed directly above the first on-chip metal pad;
a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad;
a second landing pad disposed directly above the second on-chip metal pad;
a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and
at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad.

2 . The semiconductor device according to claim 1 , wherein the first on-chip metal pad is an aluminum pad.

3 . The semiconductor device according to claim 2 , wherein the second on-chip metal pad is an aluminum pad.

4 . The semiconductor device according to claim 1 , wherein the passivation layer comprises silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.

5 . The semiconductor device according to claim 1 , wherein the first landing pad and the first via are composed of copper.

6 . The semiconductor device according to claim 5 , wherein the second landing pad and the second via are composed of copper.

7 . The semiconductor device according to claim 1 , wherein the at least five traces comprise two intervening reference traces between three high-speed signal traces to thereby form a SGSGS RDL trace configuration.

8 . The semiconductor device according to claim 7 , wherein the high-speed signal traces are operated greater than 1 Gb/s.

9 . The semiconductor device according to claim 7 , wherein the two intervening reference traces transmit a ground signal.

10 . The semiconductor device according to claim 1 , wherein the first landing pad and the second landing pad both have a rectangular shape or oval shape when viewed from the above.

11 . The semiconductor device according to claim 10 , wherein the first landing pad and the second landing pad both have an aspect ratio ranging between 1˜3.

12 . The semiconductor device according to claim 1 , wherein the first on-chip metal pad and the second on-chip metal pad have a rectangular shape or oval shape when viewed from the above.

13 . The semiconductor device according to claim 12 , wherein the first on-chip metal pad and the second on-chip metal pad both have an aspect ratio ranging between 1˜3.

14 . The semiconductor device according to claim 12 , wherein at least four aluminum traces extending along a die-to-die direction are disposed between the first on-chip metal pad and the second on-chip metal pad.

15 . A wafer level package, comprising:
an integrated circuit (IC) die having an active surface, wherein at least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface; a passivation layer on the active surface and covering the first on-chip metal pad and the second on-chip metal pad; a molding compound encapsulating the IC die except for the active surface; and a redistribution layer (RDL) structure on the passivation layer and on the molding compound, the RDL structure comprising:
a first landing pad disposed directly above the first on-chip metal pad;
a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad;
a second landing pad being disposed directly above the second on-chip metal pad;
a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and
at least three traces being disposed on the RDL structure and passing through a space between the landing pad and the second landing pad.

16 . The wafer level package according to claim 15 , wherein the first on-chip metal pad is an aluminum pad.

17 . The wafer level package according to claim 16 , wherein the second on-chip metal pad is an aluminum pad.

18 . The wafer level package according to claim 15 , wherein the passivation layer comprises silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.

19 . The wafer level package according to claim 15 , wherein the first landing pad and the first via are composed of copper.

20 . The wafer level package according to claim 19 , wherein the second landing pad and the second via are composed of copper.

21 . The wafer level package according to claim 15 , wherein the at least five traces comprise two intervening reference traces between three high-speed signal traces to thereby form a SGSGS RDL trace configuration.

22 . The wafer level package according to claim 21 , wherein the high-speed signal traces are operated greater than 1 Gb/s.

23 . The wafer level package according to claim 21 , wherein the two intervening reference traces transmit a ground signal.

24 . The wafer level package according to claim 15 , wherein the first landing pad and the second landing pad both have a rectangular shape or oval shape when viewed from the above.

25 . The wafer level package according to claim 24 , wherein the first landing pad and the second landing pad both have an aspect ratio ranging between 1˜3.

26 . The wafer level package according to claim 15 , wherein the first on-chip metal pad and the second on-chip metal pad have a rectangular shape or oval shape when viewed from the above.

27 . The wafer level package according to claim 26 , wherein the first on-chip metal pad and the second on-chip metal pad both have an aspect ratio ranging between 1˜3.

28 . The wafer level package according to claim 26 , wherein at least four aluminum traces extending along a die-to-die direction are disposed between the first on-chip metal pad and the second on-chip metal pad.

Assignees

• Mediatek Inc

Inventors

• Syu Shih-Yi
• Hsieh Tung-Hsien
• Chou Che-Ya

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/853

  On the same surface · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title