Modular magnetoresistive memory

Patent metadata

Field	Value
Publication number	US-10242725-B2
Application number	US-201715694139-A
Country	US
Kind code	B2
Filing date	Sep 1, 2017
Priority date	Sep 12, 2007
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Apparatus and method contemplating a magnetoresistive memory apparatus having a read element having a high resistance material selected to optimize read sensitivity and a write element having a material selected for a lower critical current response than the read element critical current response to optimize switching efficiency, wherein the read element resistance is higher than the write element resistance, and a shared storage space for both elements.

First claim

What is claimed is:

1. A method comprising:
obtaining a magnetoresistive memory apparatus having a read element constructed of a high resistance material selected to optimize read sensitivity, a write element constructed of a material selected for a lower critical current response than the read element critical current response to optimize switching efficiency, wherein the read element resistance is higher than the write element resistance, and the magnetoresistive memory apparatus further having a shared storage space for both the read element and the write element;
energizing the write element with a write current having a first amperage to write data to the shared storage space; and
energizing the read element with a read current having a second amperage lower than the first amperage to read data from the shared storage space.

2. The method of claim 1 wherein the obtaining step comprises the read element constructed as a tunneling magnetoresistive (TMR) stack.

3. The method of claim 1 wherein the obtaining step comprises the write element constructed as a giant magnetoresistive (GMR) stack.

4. The method of claim 2 wherein the obtaining step comprises the TMR stack including a pinned layer.

5. The method of claim 4 wherein the obtaining step comprises the TMR stack including a barrier layer.

6. The method of claim 5 wherein the obtaining step comprises the GMR stack including a second pinned layer and a spacer layer.

7. The method of claim 6 wherein the obtaining step comprises pinning at least one of the pinned layers parallel to their major planes.

8. The method of claim 6 wherein the obtaining step comprises pinning at least one of the pinned layers perpendicular to their major planes.

9. The method of claim 1 wherein the energizing steps comprise transmitting the read current and the write current to a first contact adjacent the read element and to a second contact adjacent the write element.

10. The method of claim 1 wherein the energizing steps comprise transmitting the read current to a first contact adjacent the read element and to a second contact connected to the shared storage space.

11. The method of claim 1 wherein the energizing steps comprise transmitting the write element to a first contact adjacent the write element and to a second contact connected to the shared storage space.

12. The method of claim 1 wherein the obtaining step comprises the write element including a nanocontact to the shared storage space.

13. The method of claim 1 wherein the obtaining step comprises the shared storage space divided into a plurality of separated storage portions.

14. The method of claim 13 wherein the obtaining step comprises including an electrical contact to one of the plurality of separated storage portions.

15. The method of claim 1 wherein the obtaining step comprises a plurality of shared storage spaces.

16. The method of claim 15 wherein the obtaining step comprises a plurality of the shared storage spaces each divided into a plurality of separated storage portions.

17. The method of claim 16 wherein the obtaining step comprises including an electrical contact to each of the plurality of separated storage portions.

Assignees

• Seagate Technology Llc

Inventors

• Mryasov Oleg N
• Ambrose Thomas F
• Scholz Werner

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/165 Primary

  Auxiliary circuits · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title