Semiconductor package with a through port for sensor applications

US10549985B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10549985-B2
Application numberUS-201715692938-A
CountryUS
Kind codeB2
Filing dateAug 31, 2017
Priority dateNov 25, 2016
Publication dateFeb 4, 2020
Grant dateFeb 4, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor package, comprising: a semiconductor die having a sensor structure disposed at a first side of the semiconductor die; and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, the first port providing a link between the sensor structure and the outside environment, wherein the first port comprises a larger diameter hole extending from the second side towards the first side and terminating prior to reaching the sensor structure, and a plurality of smaller diameter holes extending from the first side towards the second side and disposed around the sensor structure, wherein the smaller diameter holes are in open communication with the larger diameter hole in a region of the semiconductor die outside the sensor structure. 2. The semiconductor package of claim 1 , further comprising a cap/lid attached to the first side of the semiconductor die and covering the sensor structure and the smaller diameter holes. 3. The semiconductor package of claim 1 , further comprising a substrate to which the semiconductor die is attached at the second side, wherein the substrate has an opening at least partly aligned with the first port. 4. The semiconductor package of claim 1 , further comprising: a cap/lid attached to the first side of the semiconductor die and covering the sensor structure; and a mold compound encapsulating the cap/lid and the first side of the semiconductor die. 5. The semiconductor package of claim 4 , further comprising: a substrate attached to the mold compound; and electrical conductors extending from the first side of the semiconductor die to the substrate through the mold compound. 6. The semiconductor package of claim 4 , further comprising a leadframe attached to the second side of the semiconductor die, wherein the leadframe has an opening at least partly aligned with the first port. 7. The semiconductor package of claim 4 , further comprising: a substrate attached to the second side of the semiconductor die; a second port extending through the semiconductor die from the first side to the second side outside the sensor structure; and an opening in the mold compound which extends to the first side of the semiconductor die and is at least partly aligned with the second port, wherein the second port is in open communication with the first port. 8. The semiconductor package of claim 4 , further comprising through-mold interconnects which extend through the mold compound and connect bond pads of the semiconductor die to a redistribution layer on the mold compound. 9. The semiconductor package of claim 8 , wherein the mold compound and the through-mold interconnects terminate at the same planarized level at a side of the mold compound facing away from the semiconductor die. 10. The semiconductor package of claim 1 , wherein the sensor structure is a MEMS sensor structure. 11. The semiconductor package of claim 1 , further comprising: an interposer attached to the first side of the semiconductor die and covering the sensor structure; and a mold compound encapsulating the interposer and the first side of the semiconductor die. 12. The semiconductor package of claim 11 , further comprising a redistribution layer on the mold compound and the interposer, wherein the interposer provides electrical connections between the semiconductor die and the redistribution layer. 13. The semiconductor package of claim 12 , wherein the mold compound and the interposer terminate at the same planarized level at a side of the mold compound facing away from the semiconductor die. 14. A semiconductor package, comprising: a semiconductor die having a sensor structure disposed at a first side of the semiconductor die; and a plurality of separate trenches extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, the plurality of separate trenches forming spring structures around the sensor structure which decouple the sensor structure from mechanical stresses, wherein the plurality of separate trenches provides a link between the sensor structure and the outside environment. 15. The semiconductor package of claim 14 , wherein the sensor structure is a MEMS sensor structure.

Assignees

Inventors

Classifications

  • Pressure sensors · CPC title

  • suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound · CPC title

  • between the MEMS die and the substrate · CPC title

  • Interconnections between the MEMS and external electrical signals · CPC title

  • between the package lid and the substrate · CPC title

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Frequently asked questions

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What does patent US10549985B2 cover?
A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification B81B7/0058. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Feb 04 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).