Chip package and method thereof

Patent metadata

Field	Value
Publication number	US-9334156-B2
Application number	US-201514747507-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Aug 11, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

First claim

What is claimed is:

1. A chip package, comprising:
a semiconductor chip having at least one sensing device and at least one conductive pad electrically connected to the at least one sensing device;
an interposer disposed on the semiconductor chip, the interposer having at least one trench and at least one through hole, the trench penetrating the interposer, and the through hole exposing the conductive pad;
a polymer adhesive supporting layer interposed between the semiconductor chip and the interposer;
a redistribution layer disposed on the interposer and in the through hole to be electrically connected to the conductive pad; and
a packaging layer covering the interposer and the redistribution layer, the packaging layer having an opening exposing the trench.

2. The chip package of claim 1 , wherein the polymer adhesive supporting layer has an opening connected to the through hole to expose the conductive pad.

3. The chip package of claim 1 , wherein the polymer adhesive supporting layer comprises a thermal curing material, an ultraviolet curing material, or a combination thereof.

4. The chip package of claim 3 , wherein the polymer adhesive supporting layer comprises epoxy.

5. The chip package of claim 1 , wherein the at least one sensing device is disposed in an active region of the semiconductor chip, the conductive pad being disposed in a periphery region of the semiconductor chip, and the periphery region surrounding the active region.

6. The chip package of claim 1 , wherein the packaging layer does not fully fill the through hole.

7. The chip package of claim 1 , further comprising a conductive external connection disposed on the interposer, and the conductive external connection being electrically connected to the redistribution layer.

8. The chip package of claim 1 , wherein the interposer comprises:
a first isolation layer disposed at a lower surface of the interposer; and
a second isolation layer disposed at an upper surface of the interposer and at a sidewall of the through hole.

9. The chip package of claim 5 , wherein a projection of the trench on the semiconductor chip is in at least one side of the active region.

10. The chip package of claim 1 , wherein the polymer adhesive supporting layer is a polymer dam structure.

11. A method of manufacturing a chip package, comprising:
forming a first isolation layer at a lower surface of an interposer;
forming at least one trench extending in a direction from the lower surface to an upper surface of the interposer;
forming a polymer adhesive supporting layer under the lower surface, and the polymer adhesive supporting layer having an opening;
binding the interposer and a semiconductor chip via the polymer adhesive supporting layer, the semiconductor chip having at least one sensing device and at least one conductive pad electrically connected to the at least one sensing device, and the opening of the polymer adhesive supporting layer corresponding to the conductive pad;
forming at least one through hole extending from the upper surface to the lower surface and through the opening of the polymer adhesive supporting layer to expose the conductive pad;
forming a second isolation layer covering the upper surface and a sidewall of the through hole;
forming a redistribution layer on the second isolation layer and in the through hole to be electrically connected to the conductive pad;
etching the interposer to expose the trench at the upper surface; and
forming a packaging layer covering on the redistribution layer, and the packaging layer having an opening exposing the trench.

12. The method of manufacturing the chip package of claim 11 , wherein forming the polymer adhesive supporting layer at the lower surface comprises:
coating the polymer adhesive supporting layer at the lower surface; and
photolithography etching the polymer adhesive supporting layer to form the opening in the polymer adhesive supporting layer.

13. The method of manufacturing the chip package of claim 12 , further comprising:
thinning the interposer from the upper surface between the step of binding the interposer and the semiconductor chip via the polymer adhesive supporting layer and the step of forming the through hole extending from the upper surface to the lower surface and through the opening of the polymer adhesive supporting layer to expose the conductive pad.

14. The method of manufacturing the chip package of claim 11 , wherein forming the packaging layer covering on the redistribution layer comprises:
coating the packaging layer on the redistribution layer; and
laser drilling the packaging layer to form the opening in the packaging layer to expose the trench.

15. The method of manufacturing the chip package of claim 14 , wherein the packaging layer does not fully fill the through hole during coating the packaging layer on the redistribution layer.

16. The method of manufacturing the chip package of claim 11 , wherein the polymer adhesive supporting layer comprises a thermal curing material, an ultraviolet curing material, or a combination thereof.

17. The method of manufacturing the chip package of claim 16 , wherein the thermal curing material comprises epoxy.

18. The method of manufacturing the chip package of claim 11 , further comprising:
forming a conductive external connection on the interposer, and the conductive external connection being electrically connected to the redistribution layer.

19. The method of manufacturing the chip package of claim 11 , wherein the polymer adhesive supporting layer is a polymer dam structure.

Assignees

• Xintec Inc

Inventors

• Lin Chien-Min
• Huang Yu-Ting
• Fu Chen-Ning
• Ho Yen-Shih

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title