Gate contact structure positioned above an active region of a transistor device

Patent metadata

Field	Value
Publication number	US-10243053-B1
Application number	US-201815876316-A
Country	US
Kind code	B1
Filing date	Jan 22, 2018
Priority date	Jan 22, 2018
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

One illustrative IC product disclosed herein includes a gate structure for a transistor, a conductive source/drain contact structure and an insulating source/drain cap structure positioned above the conductive source/drain contact structure, wherein the insulating source/drain cap structure has a first notch formed therein. In one illustrative example, the product also includes a sidewall spacer that has a second notch in an upper portion of the sidewall spacer, wherein a first portion of the insulating source/drain cap structure is positioned in the second notch, and a conductive gate contact structure comprising first and second portions, the first portion of the conductive gate contact structure being positioned in the first notch and the second portion of the conductive gate contact structure being in contact with the gate structure.

First claim

What is claimed:

1. An integrated circuit product, comprising:
a gate structure for a transistor;
a conductive source/drain contact structure;
an insulating source/drain cap structure positioned above said conductive source/drain contact structure, said insulating source/drain cap structure comprising a first notch;
a sidewall spacer, a portion of which is positioned laterally between said gate structure and said conductive source/drain contact structure, said sidewall spacer comprising a second notch in an upper portion of said sidewall spacer, wherein a first portion of said insulating source/drain cap structure is positioned in said second notch; and
a conductive gate contact structure comprising first and second portions, said first portion of said conductive gate contact structure being positioned in said first notch, said second portion of said conductive gate contact structure being in contact with said gate structure.

2. The integrated circuit product of claim 1 , wherein said sidewall spacer comprises a tapered portion that is positioned laterally between a part of said conductive gate contact structure and a part of said insulating source/drain cap structure.

3. The integrated circuit product of claim 1 , wherein, when said insulating source/drain cap structure is viewed in a cross-section taken in a direction corresponding to a gate length direction of said transistor, said first notch is defined, at least in part, by an upper surface connected by a first tapered surface to a first substantially horizontally oriented surface positioned at a first height less than a second height of said upper surface.

4. The integrated circuit product of claim 3 , wherein said first portion of said conductive gate contact structure physically contacts said first tapered surface and said first substantially horizontally oriented surface.

5. The integrated circuit product of claim 1 , wherein, when said sidewall spacer is viewed in a cross-section taken in a direction corresponding to a gate length direction of said transistor, said second notch is defined, at least in part, by an upper surface, a second tapered surface extending between said upper surface and a second substantially horizontally oriented surface positioned at a first height less than a second height of said upper surface.

6. The integrated circuit product of claim 5 , wherein said first portion of said insulating source/drain cap structure physically contacts said second tapered surface and said second substantially horizontally oriented surface.

7. The integrated circuit product of claim 5 , wherein said first portion of said insulating source/drain cap structure is positioned vertically between said first portion of said conductive gate contact structure and said second substantially horizontally oriented surface.

8. The integrated circuit product of claim 1 , wherein said first notch is positioned vertically above an active region of said transistor.

9. The integrated circuit product of claim 1 , wherein said conductive gate contact structure is conductively coupled to a gate structure of at least one additional transistor.

10. The integrated circuit product of claim 1 , wherein said transistor is a FinFET transistor.

11. The integrated circuit product of claim 1 , further comprising a gate cap positioned above said gate structure, wherein said gate cap is comprised of a first material and said sidewall spacer is comprised of a second material that is different than said first material, wherein, when subjected to a common etching process, said first material has a first etch rate and said second material has a second etch rate, said second etch rate being greater than said first etch rate.

12. The integrated circuit product of claim 11 , wherein said first material is silicon nitride and said second material is silicon carbon nitride (SiCoN).

13. The integrated circuit product of claim 1 , wherein said sidewall spacer physically contacts both said gate structure and said conductive source/drain contact structure.

14. An integrated circuit product, comprising:
a gate structure for a transistor;
a conductive source/drain contact structure;
an insulating source/drain cap structure positioned above said conductive source/drain contact structure, said insulating source/drain cap structure comprising a first notch;
a sidewall spacer, a portion of which is positioned laterally between said gate structure and said conductive source/drain contact structure, said sidewall spacer comprising a second notch in an upper portion of said sidewall spacer that is at least partially defined by a tapered portion, wherein a first portion of said insulating source/drain cap structure is positioned in said second notch and physically contacts said sidewall spacer; and
a conductive gate contact structure comprising first and second portions, wherein said first portion of said conductive gate contact structure is positioned in said first notch and physically contacts said insulating source/drain cap structure, said second portion of said conductive gate contact structure is in contact with an upper surface of said gate structure and wherein said tapered portion of said sidewall spacer is positioned laterally between a part of said conductive gate contact structure and a part of said insulating source/drain cap structure.

15. The integrated circuit product of claim 14 , wherein, when said insulating source/drain cap structure is viewed in a cross-section taken in a direction corresponding to a gate length direction of said transistor, said first notch is defined, at least in part, by an upper surface connected by a first tapered surface to a first substantially horizontally oriented surface positioned at a first height less than a second height of said upper surface.

16. The integrated circuit product of claim 15 , wherein said first portion of said conductive gate contact structure physically contacts said first tapered surface and said first substantially horizontally oriented surface.

17. The integrated circuit product of claim 14 , wherein, when said sidewall spacer is viewed in a cross-section taken in a direction corresponding to a gate length direction of said transistor, said second notch is defined, at least in part, by an upper surface, a second tapered surface extending between said upper surface and a second substantially horizontally oriented surface positioned at a first height less than a second height of said upper surface.

18. The integrated circuit product of claim 17 , wherein said first portion of said insulating source/drain cap structure physically contacts said second tapered surface and said second substantially horizontally oriented surface.

19. The integrated circuit product of claim 14 , wherein said first portion of said insulating source/drain cap structure is positioned vertically between said first portion of said conductive gate contact structure and a substantially horizontally oriented surface that at least partially defines said second notch.

20. The integrated circuit product of claim 14 , wherein said first notch is positioned vertically above an active region of said transistor.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Labonte Andre
• Park Chanro

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title