Scalable circuit-under-pad device topologies for lateral GaN power transistors

Patent metadata

Field	Value
Publication number	US-10529802-B2
Application number	US-201815988453-A
Country	US
Kind code	B2
Filing date	May 24, 2018
Priority date	Sep 14, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

First claim

The invention claimed is:

1. A semiconductor device structure comprising:
a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multi-section transistor;
each transistor section comprising source, drain and gate electrodes defined on the active region;
a level of on-chip metallization defining for each section a contact structure comprising a drain contact area and first and second source contact areas;
the drain contact area comprising a drain pad extending over a part of the active region located between the first and second source contact areas;
the drain pad being interconnected by conductive micro-vias to underlying parts of the drain electrodes and
the first and second source contact areas being interconnected to the source electrodes,
the first and second source contact areas comprising first and second parts of a split source pad, the drain pad extending over a central part of the active region of the section, and the first and second parts of the split source pad being located each side of the drain pad, overlying the active region, and interconnected by conductive micro-vias to underlying parts of the source electrodes, and
a gate bus interconnecting gate electrodes of each section, the gate bus running in inactive regions between sections, and at least part of the first and second parts of the split source pad extending over the gate bus.

2. The semiconductor device structure of claim 1 , wherein the drain pad has an area which is larger than an area of the split source pad.

3. The semiconductor device structure of claim 2 , wherein the drain electrodes have a first cross-section and the source electrodes have a second cross-section greater than the first cross-section, and wherein said areas of the drain pad and first and second parts of the split source pad are sized in proportion to said first and second cross-sections.

4. The semiconductor device structure of claim 3 , wherein neighbouring edges of the drain pad and the first and second parts of the split source pad are castellated.

5. A semiconductor device structure comprising:
a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multi-section transistor;
each transistor section comprising source, drain and gate electrodes defined on the active region;
a level of on-chip metallization defining for each section a contact structure comprising a drain contact area and first and second source contact areas;
the drain contact area comprising a drain pad extending over a part of the active region located between the first and second source contact areas;
the drain pad being interconnected by conductive micro-vias to underlying parts of the drain electrodes and
the first and second source contact areas being interconnected to the source electrodes,
the first and second source contact areas comprising first and second parts of a split source pad, the drain pad extending over a central part of the active region of the section, and the first and second parts of the split source pad being located each side of the drain pad, overlying the active region, and interconnected by conductive micro-vias to underlying parts of the source electrodes, and
a gate bus interconnecting gate electrodes of each section, the gate bus running in inactive regions between sections, and wherein the first and second parts of the split source pad extend over the gate bus and are contiguous with first and second parts of the split source pads of neighbouring sections.

6. The semiconductor device structure of claim 5 , wherein the drain pad has an area which is larger than an area of the split source pad.

7. The semiconductor device structure of claim 6 , wherein the drain electrodes have a first cross-section and the source electrodes have a second cross-section greater than the first cross-section, and wherein said areas of the drain pad and first and second parts of the split source pad are sized in proportion to said first and second cross-sections.

8. The semiconductor device structure of claim 7 , wherein neighbouring edges of the drain pad and the first and second parts of the split source pad are castellated.

9. A semiconductor device structure comprising a lateral GaN (gallium nitride) power transistor comprising:
a substrate comprising a device area of the transistor;
a nitride semiconductor layer formed on the device area of the substrate, the nitride semiconductor layer comprising a GaN heterostructure defining active regions for a plurality of transistor sections of a multi-section transistor;
a first level of on-chip metallization (M1), M1 being patterned to define source, drain and gate finger electrodes of each transistor section and a gate bus; for each section, the gate bus comprising a first portion formed on an inactive region along a first edge of the active region, and second portions of the gate bus extending from the first portion of the gate bus and formed on inactive regions between active regions of each section;
in each section, the source and drain finger electrodes being arranged as an array with the gate finger electrodes running in channel regions between adjacent source and drain finger electrodes, and the gate finger electrodes being interconnected to adjacent second portions of the gate bus;
an overlying second level of on-chip metallization (M2), M2 being patterned to define for each section a contact structure comprising a drain pad and first and second source contact areas, in each section the drain pad extending over a central part of the active region, and the first and second source contact areas being located each side of the drain pad;
an intermetal dielectric layer provided between the first and second level metallization M1 and M2;
the drain pad being interconnected by conductive micro-vias through the intermetal dielectric layer to underlying drain finger electrodes; and
the first and second source contact areas being interconnected to the source finger electrodes.

10. The semiconductor device structure of claim 9 , wherein the first and second source contact areas comprise first and second parts of a split source pad (first and second source pads), which are contiguous with the source pads of adjacent sections, and part of the first and second source pads is routed over said second portions of the gate bus for reduced gate loop inductance.

11. The semiconductor device structure of claim 9 , wherein the first and second source contact areas comprise first and second parts of a split source pad (first and second source pads), wherein the first and second source pads are spaced from neighbouring source pads of adjacent sections.

12. The semiconductor device structure of claim 11 , wherein part of the first and second source pads is routed over said second portions of the gate bus for reduced gate loop inductance.

13. The semiconductor device structure of claim 11 , wherein the first and second source pads are formed over the active region without overlapping the gate bus.

14. The semiconductor device structure of claim 9 , wherein the contact structure comprises a three-piece pad structure comprising one drain pad and first and second source pads for each section,
in each section, the drain pad being centered over the active region and extending laterally in a width direction over a central part of the active region of the section,
the first and second source pads being defined each side of the drain pad, each extending laterally over the active region of the section between the drain pad and an adjacent second portion of the gate bus, later

Assignees

• Gan Systems Inc

Inventors

• Mizan Ahmad
• Mousavian Hossein
• Cui Xiaodong

Classifications

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/402

  Electricity · mapped topic

• H01L29/41758

  Electricity · mapped topic