Gallium nitride power devices using island topography

Patent metadata

Field	Value
Publication number	US-9508797-B2
Application number	US-201514681676-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Aug 4, 2009
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes.

First claim

What is claimed is:

1. A nitride semiconductor device comprising:
a substrate;
a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;
a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged as an array with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer;
a plurality of gate strip electrodes formed on the nitride semiconductor layer in active regions between adjacent source island electrodes and drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes;
each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump, ball or post connection formed thereon;
each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump, ball or post connection formed thereon;
the low resistance gate interconnect being connected to a plurality of gate pads; and
wherein, in defective active regions, individual gate strip electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.

2. The nitride semiconductor device of claim 1 , wherein in defective active regions, individual drain island electrodes are isolated by absence or removal of the bump, ball or post connection thereon.

3. The nitride semiconductor device of claim 1 , wherein each of the plurality of source island electrodes comprises a plurality of castellated peninsulas extending from at least one side, which are interleaved with a plurality of castellated peninsulas extending from a side of an adjacent one of the plurality of drain island electrodes.

4. The nitride semiconductor device of claim 1 , wherein the first and second island electrodes:
a) have a predominantly rectangular shape; or
b) have a predominantly triangular shape; or
c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.

5. The nitride semiconductor device of claim 1 , wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AlGaN).

6. The nitride semiconductor device of claim 5 further comprising a layer of p-type GaN material or p-type AlGaN material under the gate electrode to create an enhancement-mode device.

7. A nitride semiconductor device comprising:
a substrate;
a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;
a metallization layer formed on the nitride semiconductor layer defining a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged as an array with alternating first island electrodes and second island electrodes along at least two orthogonal directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with
at least one side of each first island electrode opposite a side of an adjacent second island electrode;
at least one side of each second island electrode opposite a side of an adjacent first island electrode;
an overlying interconnect structure comprising one or more metallization layers and intervening insulating layers;
the one or more metallization layers of the overlying interconnect structure defining a plurality of first common electrodes and a plurality of second common electrodes, the first common electrodes and the second common electrodes being arranged as a second array with alternating first common electrodes and second common electrodes, the second array of first and second common electrodes overlying the array of the first and second island electrodes;
each first common electrode being interconnected to a set of said first island electrodes by said one or more metallization layers and conductive vias; and
each second common electrode being interconnected to a set of said second island electrodes by said one or more metallization layers and conductive vias;
each of the first common electrodes providing an external first connection formed thereon comprising a ball, bump or post connection, and
each of the second common electrodes comprises an external first connection formed thereon comprising a ball, bump or post connection;
the first island electrodes and second island electrodes serving, respectively, as source island electrodes and drain island electrodes of a multi-island transistor; and
a plurality of gate strip electrodes of the multi-island transistor formed on the nitride semiconductor layer in active regions between adjacent first island electrodes and second island electrodes;
a low resistance gate interconnect running between the source island electrodes and drain island electrodes overlying the gate strip electrodes, the plurality of gate strip electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the first island electrodes and second island electrodes;
one or more gate common electrodes comprising an external gate connection formed thereon comprising a ball, bump or post connection; and
the gate strap connecting the interconnected gate strip electrodes to the one or more gate common electrodes; and
wherein, in defective active regions, individual gate electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.

8. The nitride semiconductor device of claim 7 ,
wherein in said defective active regions, individual drain common electrodes are isolated by absence or removal of the bump, ball or post connection thereon.

9. The nitride semiconductor device of claim 7 , wherein the first and second island electrodes:
a) have a predominantly rectangular shape; or
b) have a predominantly triangular shape; or
c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.

10. The nitride semiconductor device of claim 7 wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AlGaN).

11. The nitride semiconductor device of claim 10 further comprising a layer of p-type GaN material or p-type AlGaN material under the gate electrode to create an enhancement-mode device.

12. A nitride semiconductor device comprising:
a substrate;
a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;
a plurality of source, drain and gate electrodes of a multi-island transistor formed on the nitride semiconductor layer, the plurality of source, drain and gate electrodes comprising concentric electrode islands of decreasing size and arranged as repeated square shaped concentric tracks of ohmic and Schottky contacts, every two ohmic

Assignees

• Roberts John
• Mizan Ahmad
• Patterson Girvan
• Klowak Greg
• Gan Systems Inc

Inventors

• Roberts John
• Mizan Ahmad
• Patterson Girvan
• Klowak Greg

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/254

  for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title