Packaging solutions for devices and systems comprising lateral GaN power transistors

Patent metadata

Field	Value
Publication number	US-9589869-B2
Application number	US-201615064955-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 11, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

First claim

The invention claimed is:

1. A semiconductor device structure comprising an assembly of:
a lateral Gallium Nitride power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising first and second leadframe layers;
the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;
the GaN die being sandwiched between the first and second leadframe layers;
the first leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;
the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die;
the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material;
the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the first leadframe layer by low inductance interconnections; and
a package body comprising an over-molding of encapsulation which leaves exposed the thermal pad of the second leadframe layer and leaves exposed external contact pads for the source, drain and gate of the lateral GaN transistor.

2. The device structure of claim 1 , wherein the external pads for the source, drain and gate contacts are part of the first leadframe layer and are provided on one side of the package body and the thermal pad is provided on an opposite side of the package body.

3. The device structure of claim 2 , wherein the second leadframe comprising the thermal pad further comprises a source clip, which extends laterally of the die substrate, and is vertically interconnected to the source portion of the first leadframe layer, thereby providing a substrate source connection for grounding the die substrate to the source.

4. The device structure of claim 1 , wherein the second leadframe layer comprises source, drain and gate portions, and the external contact pads for the source, drain and gate comprise part of the respective source, drain and gate portions of the second leadframe layer; and wherein the respective source, drain and gate portions of the first and second leadframe layers are vertically interconnected, within the package body, by low inductance interconnections comprising a layer of electrically and thermally conductive material, and each of the external pads for the source, gate and drain contacts and the thermal pad are provided on one side of the package body.

5. The device structure of claim 4 , wherein the thermal pad is part of the source portion of the second leadframe layer and is grounded to the source portion of the first leadframe layer within the package body, such that the thermal pad provides the external pad for the source contact, and the drain and gate portions of the second leadframe layer are electrically connected to respective drain and source portions of the first leadframe layer, said drain and gate portions of the second leadframe layer providing external pads for drain and gate contacts on the same side of the package body as the external pad providing the source contact and thermal pad.

6. The device structure of claim 5 , wherein the second leadframe layer comprising the thermal pad further comprises a source clip, which extends laterally of the die substrate and is vertically interconnected to the source portion of the first leadframe layer, thereby providing a substrate-source connection for grounding the die substrate to the source, wherein the exposed surface of the thermal pad acts as the substrate source contact area, and a drain clip portion of the second leadframe layer is formed laterally of the die substrate and is vertically interconnected to the drain portion of the first leadframe layer.

7. The device structure of claim 6 , wherein the drain clip portion provides a drain contact area coplanar with the surface of the thermal pad which provides the source contact area.

8. The device structure claim 1 , wherein the semiconductor substrate of the GaN die comprises a silicon substrate, and wherein the first and second leadframe layers comprise copper and/or a copper alloy with high electrical and thermal conductivity.

9. The device structure of claim 8 , wherein the attachment material attaching the back surface of the GaN die to the die-attach area of the second leadframe layer comprises a layer of sintered silver.

10. The device structure of claim 1 , wherein the semiconductor substrate of the GaN die comprises a silicon carbide substrate, wherein the first and second leadframe layers each comprise copper and/or a copper alloy with high electrical and thermal conductivity.

11. The device structure of claim 10 , wherein the attachment material attaching the back surface of the GaN die to the die-attach area of the second leadframe layer comprises a layer of sintered silver.

12. The device structure of claim 1 , wherein the low inductance interconnections comprise metal bump or metal post connections.

13. The device structure of claim 12 , wherein the metal bump or metal post connections comprise copper pillars.

14. The device structure claim 1 , wherein the semiconductor substrate of the GaN die comprises a silicon substrate, the first and second leadframe layers comprise copper and/or a copper alloy with high electrical and thermal conductivity, the attachment material comprises sintered silver, and the low inductance interconnections comprises solder tipped copper pillars.

15. The device structure of claim 1 , wherein the first and second leadframe layers further comprising registration means for laterally and vertically aligning the first and second leadframe layers during assembly.

16. The device structure of claim 15 , wherein the registration means comprises tabs on the first copper leadframe layer and corresponding slots in the second copper leadframe layer, the tabs and slots inter-engaging to mutually align the first and second leadframes.

17. The device structure of claim 15 , wherein the registration means comprises tabs on the second copper leadframe layer and corresponding slots in the first copper leadframe layer, the tabs and slots inter-engaging to mutually align first and second leadframes.

18. The device structure of claim 1 , further comprising a second lateral GaN die or other semiconductor die co-packaged with the said GaN die and interconnected therewith by said first and second leadframe layers.

19. A method of fabricating a semiconductor device structure comprising an assembly of: a lateral Gallium Nitride power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising first and second leadframe layers encapsulated within a package body, the method comprising:
providing the GaN die comprising a front surface comprising source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;
providing a first leadframe layer and a second leadframe layer;
the first leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;
the second leadframe layer providing a die-attach area for the back surface of the GaN die and a thermal pad;
attaching the back surface of the GaN die to the die-attach area of the second leadframe layer w

Assignees

• Gan Systems Inc

Inventors

• Mcknight-Macneil Cameron
• Klowak Greg P
• Mizan Ahmad

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title