Distributed driver circuitry integrated with GaN power transistors

Patent metadata

Field	Value
Publication number	US-9660639-B2
Application number	US-201615091867-A
Country	US
Kind code	B2
Filing date	Apr 6, 2016
Priority date	Dec 21, 2012
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D 3 ) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D 3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D 3. Each driver element is placed in proximity to a respective section of D 3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

First claim

The invention claimed is:

1. A GaN switching device comprising:
a large area lateral GaN power transistor (GaN FET) arranged as a plurality of sections, and
a distributed driver comprising a plurality of driver elements, each driver element comprising a pull-up driver transistor and a pull-down driver transistor connected in series, wherein the output of each one of the distributed driver elements is selectively connected to drive a respective one of the sections of the large GaN power transistor.

2. The GaN switching device of claim 1 , wherein the pull-down driver transistor is distributed as a plurality of pull-down driver transistor elements, each pull-down driver transistor element being arranged for driving a respective section of the GaN power transistor and wherein a single pull-up driver transistor is provided for driving all sections of the GaN power transistor.

3. The GaN switching device of claim 1 , wherein both the pull-up driver transistor and pull-down driver transistor are distributed as a plurality of distributed driver elements, each driver element comprising an individual pull-down driver transistor and an individual pull-up driver transistor in series and providing a gate output for driving its respective section of the GaN power transistor.

4. The GaN switching device of claim 1 , wherein the plurality of sections of the GaN FET and the plurality of driver elements are arranged to provide a layout wherein each one of the distributed driver elements is placed in close physical proximity to the respective one of the sections of the large GaN FET that it drives.

5. The GaN switching device of claim 1 , wherein each one of the driver elements is placed in close physical proximity to the respective one of the sections of the large GaN power switch, and wherein routing and sizing of respective interconnect tracks connecting the distributed driver elements and respective sections of GaN switch are selected to minimize loop inductance.

6. The device of claim 1 , wherein the gate output track connection of the driver element which drives a section of the gate of the large GaN power switch and the return track connection to the source of the pull-down driver transistor of the driver element are magnetically mirrored so as to reduce the loop inductance.

7. The device of claim 1 , wherein the routing and sizing of interconnect tracks for the gate output and return between each driver element and respective sections of the GaN power switch are arranged to reduce the loop inductance.

8. The device of claim 7 , wherein said tracks comprise two layer tracks arranged in parallel.

9. The device of claim 7 , wherein said tracks comprise three parallel tracks wherein a signal line is encompassed by drive lines, above and below the signal line.

10. A GaN switching device comprising:
a substrate;
an enhancement mode (E-Mode) GaN switch and an integrated GaN driver formed on the substrate;
the E-Mode GaN switch comprising a large area lateral GaN transistor switch D 3 having an active area that is partitioned into a plurality of sections (D 3 1 to D 3 n );
the integrated GaN driver being integrated monolithically on the substrate adjacent the active area of GaN transistor D 3 ; and
the integrated GaN driver being distributed as a corresponding plurality of driver elements, each driver element being located on the substrate in close proximity to a respective one of the plurality of sections of D 3 and coupled to the respective section of D 3 by low inductance interconnects.

11. A GaN switching device according to claim 10 , wherein each driver element comprises a first, pull-up E-Mode GaN driver transistor D 1 and a second, pull-down E-Mode GaN driver transistor D 2 ;
the drain of D 1 being coupled to Vcc, and the source of D 1 being coupled to the drain of D 2 at node N, which is coupled to the gate of the respective section of D 3 , and an internal source-sense connection closely coupling the source of the respective section of D 3 and the source of D 2 , such that the first transistor D 1 delivers a drive voltage to the gate of the respective section of the GaN transistor switch D 3 , and the second transistor D 2 clamps the gate of the respective section the GaN transistor switch D 3 by means of the internal source-sense connection SS internal ;
inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D 1 and D 2 of each driver element and optionally to the gates of each section of D 3 , and
an external source-sense connection SS external for coupling to the pre-driver.

12. The device of claim 10 , wherein each section D 3 n of D 3 has a respective individual driver element comprising a pull-up driver element D 1 n , and a pull-down driver element D 2 n .

13. The device of claim 10 , wherein each section D 3 n of D 3 is coupled to a respective individual pull-down driver element D 1 n , and wherein a single pull-up driver element D 2 is coupled to the plurality of sections of D 3 .

14. The device of claim 11 , wherein each section D 3 n of D 3 has a respective individual driver element comprising a pull-up driver D 1 n and a pull-down driver D 2 n .

15. The device of claim 11 , wherein each section D 3 n of D 3 is coupled to a respective individual pull-down driver element D 1 n , and wherein a single pull-up driver element D 2 is coupled to a plurality of sections of D 3 .

Assignees

• Gan Systems Inc

Inventors

• Roberts John
• Mizan Ahmad

Classifications

• H03K17/6877

  the control circuit comprising active elements different from those used in the output circuit · CPC title

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03K17/168

  in composite switches · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title