Embedded packaging for devices and systems comprising lateral GaN power transistors

Patent metadata

Field	Value
Publication number	US-9659854-B2
Application number	US-201515027012-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Apr 16, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

First claim

The invention claimed is:

1. A semiconductor device structure comprising:
a GaN power switching device comprising a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die);
the GaN die comprising an on-chip metallization layer defining source, drain and gate contact areas on a front-side of the GaN die, said source and drain contact areas being distributed over an active area of the lateral GaN power transistor and providing a first level of interconnect to a plurality of underlying source and drain electrodes of the lateral GaN power transistor;
an overlying second level of interconnect comprising a dielectric layer formed on the GaN die defining contact openings to the underlying source, drain and gate contact areas of the on-chip metallization layer and a second metallization layer formed thereon defining a source contact area, a drain contact area and one or more gate contact areas, the thickness and lateral dimensions of the source contact area and drain contact area of the second metallization layer being greater than those of the underlying source and drain contact areas of the on-chip metallization layer; and
packaging components comprising one or more dielectric layers forming a dielectric body of a package and package metallization;
the GaN chip and overlying second level of interconnect being embedded in the dielectric body of the package with the dielectric body of the package extending laterally around the GaN die;
the package metallization comprising:
an overlying metal layer and an underlying metal layer sandwiching the dielectric body of the package, the overlying metal layer extending over a front-side of the dielectric body and the underlying metal layer extending over a back-side of the dielectric body,
the overlying metal layer being patterned to define large area source and drain contact areas extending laterally of the underlying GaN die, and one or more gate contact areas;
the underlying metal layer being patterned to define a thermal pad underlying a back-side of the GaN die, and an external source contact pad, an external drain contact pad, an external gate contact pad, an external source sense pad, each laterally spaced from the thermal pad;
the respective source, drain and gate areas of the second metallization layer on the GaN die being electrically interconnected vertically through the dielectric body of the package with the corresponding source, drain and gate contact areas of the overlying metal layer of the package metallization;
the respective source, drain and gate areas of the overlying metal layer being electrically interconnected vertically through the dielectric body of the package with corresponding external source, drain, and gate contact pads of the underlying metal layer of the package metallization; and
the back-side of the GaN die being thermally coupled to the thermal pad.

2. The device of claim 1 , wherein the back-side of the GaN die is electrically connected to the thermal pad.

3. The device of claim 1 , wherein the source contact area and drain contact area defined by the second metallization layer each comprise a plurality of tapered fingers extending laterally over respective source and drain contact areas of the on-chip metallization layer.

4. The device structure of claim 3 , wherein the overlying metal layer of package metallization comprises a corresponding plurality of tapered fingers overlying tapered fingers of the second metallization layer.

5. The device structure of claim 1 , wherein the second metallization layer comprises a copper redistribution layer.

6. The device structure of claim 1 , wherein metallization of the second level of interconnect comprises a copper redistribution layer and the dielectric comprises a polyimide dielectric.

7. The device structure of claim 1 , wherein the underlying and overlying metal layers of the package metallization each comprise a thick plated copper layer or one or more copper foil layers and the dielectric body of the package comprises one or more layers of a prepreg type dielectric.

8. The semiconductor device structure of claim 1 , wherein the dimensions metallization layers of first, second and third level interconnects increases from: typically 3 μm -100 μm laterally, and ˜5 μm thick, for the on-chip metallization; to 50 μm-500 μm laterally, and ˜5-10μm thick, for the second metallization layer; to several mm laterally, ˜40 μm or more thick, for the overlying and underlying metallization layers of third level interconnect.

9. The device structure of claim 1 , wherein the metallization of the second level interconnect comprises a copper redistribution layer (Cu RDL) and the overlying metallization layer of the package metallization comprises a copper foil layer, and the Cu RDL and overlying thicker copper layer are vertically interconnected through the dielectric body of the package by a plurality of copper pillars.

10. The device structure of claim 1 , wherein the source and drain contact areas of the overlying metallization layer and the respective back-side external source pad and external drain pad defined by the underlying metallization layer are vertically interconnected by conductive copper pillars extending through the dielectric of the package around the periphery of the package.

11. The device structure of claim 1 , wherein the back-side of the GaN die is thermally connected to the thermal pad by a plurality of copper pillars.

12. The device structure of claim 1 , wherein the GaN die comprises a GaN heterolayer structure on a silicon substrate.

13. The device structure of claim 1 , wherein the GaN die is co-packaged with a MOSFET driver chip.

14. The device structure of claim 1 , comprising a plurality of GaN die embedded within the dielectric body of the package.

15. The device structure of claim 14 wherein the plurality of GaN die are arranged to provide a half-bridge circuit.

Assignees

• Gan Systems Inc

Inventors

• Klowak Greg P
• Mizan Ahmad
• Roberts John

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title