Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above

Patent metadata

Field	Value
Publication number	US-10529720-B2
Application number	US-201916238653-A
Country	US
Kind code	B2
Filing date	Jan 3, 2019
Priority date	Jan 12, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line. Other aspects, including structure independent of method, are disclosed.

First claim

The invention claimed is:

1. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate insulator and channel material, the gate insulator comprising a laterally-outer vertical sidewall that is vertically aligned with a laterally-outer vertical sidewall of the laterally-outer electrode; wherein the laterally-outer electrode has an upwardly-open container shape and the channel material is electrically coupled to the laterally-inner electrode.

2. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate insulator and channel material, the gate insulator comprising a laterally-outer vertical sidewall that is vertically aligned with a laterally-outer vertical sidewall of the laterally-outer electrode; wherein the laterally-outer electrode comprises a downwardly-open conductive material.

3. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate insulator and channel material, the gate insulator comprising a laterally-outer vertical sidewall that is vertically aligned with a laterally-outer vertical sidewall of the laterally-outer electrode; wherein the laterally-outer electrode comprises an upwardly and downwardly-open conductive material cylinder.

4. The array of claim 1 wherein the vertical transistor further comprises a gate that surrounds the laterally-outer vertical sidewall of the gate insulator.

5. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate insulator and channel material, the gate insulator comprising a laterally-outer vertical sidewall that is vertically aligned with a laterally-outer vertical sidewall of the laterally-outer electrode; wherein the capacitor insulator comprises programmable material and the capacitor is non-volatile.

6. The array of claim 5 wherein the programmable material comprises conductive bridging RAM material.

7. The array of claim 5 wherein the programmable material comprises phase change material.

8. The array of claim 5 wherein the programmable material comprises resistive RAM material.

9. The array of claim 5 wherein the programmable material comprises ferroelectric material.

10. The array of claim 9 wherein the ferroelectric material comprises one or more of transition metal oxide, zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate.

11. The array of claim 10 wherein the ferroelectric material comprises dopant therein comprising one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and a rare-earth element.

12. The array of claim 1 wherein the capacitor insulator comprises dielectric material and the capacitor is volatile.

13. The array of claim 12 wherein the dielectric material comprises one or more of silicon dioxide, silicon nitride, aluminum oxide, and a high-k dielectric.

14. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate insulator and channel material, the gate insulator comprising a laterally-outer vertical sidewall that is vertically aligned with a laterally-outer vertical sidewall of the laterally-outer electrode; wherein the capacitor insulator comprises combination of at least one programmable material and at least one non-programmable material and the capacitor is non-volatile.

15. The array of claim 14 wherein the memory cells individually have a total of only one transistor and a total of only one capacitor.

16. The array of claim 15 wherein the memory cells individually are devoid of any other operable component.

17. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate insulator and channel material, the gate insulator comprising a laterally-outer vertical sidewall that is vertically aligned with a laterally-outer vertical sidewall of the laterally-outer electrode; wherein the memory cells individually have a total of only two transistors and a total of only one capacitor.

18. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate insulator and channel material, the gate insulator being laterally-wider at an uppermost location thereof than at a lowermost location thereof.

19. The array of claim 18 wherein 77 wherein the gate insulator comprises an annulus.

20. An array of memory cells individually comprising:
a vertical transistor electrically coupled to a capacitor;
the capacitor comprising a laterally-outer electrode, a laterally-inner electrode, and a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode; and
the vertical transistor comprising a gate, a gate-insulator annulus, and a channel-material annulus; the gate-insulator annulus comprising part of a longitudinally-elongated word line, the gate surrounding a radially-outer sidewall of the gate-insulator annulus and being horizontally thicker at a lowermost location thereof horizontally along a vertical plane through a radial center of the gate-insulator annulus orthogonal to longitudinal orientation of the word line than at a lowermost location thereof horizontally along said vertical plane.

Assignees

• Micron Technology Inc

Inventors

• Sills Scott E
• Ramaswamy Durai Vishak Nirmal

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H01L29/66666

  Electricity · mapped topic

• H01L27/1082 Primary

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic