Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor

Patent metadata

Field	Value
Publication number	US-10062745-B2
Application number	US-201715401372-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Jan 9, 2017
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.

First claim

The invention claimed is:

1. A method of forming an array of capacitors, comprising:
forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate, individual of the capacitor electrode lines being common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed;
forming a capacitor insulator over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines;
forming an elevationally-extending conductive line over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines; and
cutting laterally through the conductive line to form spaced individual other of the two capacitor electrodes of the individual capacitors.

2. The method of claim 1 wherein the forming of the elevationally-extending conductive line over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines comprises anisotropically etching conductive material of the conductive line without any mask being atop the substrate within the array and prior to the cutting.

3. The method of claim 1 comprising forming another elevationally-extending conductive line over the capacitor insulator longitudinally along the other laterally-opposing side of the individual capacitor electrode lines prior to the cutting.

4. The method of claim 1 wherein the forming of the elevationally-extending conductive line over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines comprises two time-spaced depositions of conductive material of the conductive line prior to the cutting.

5. The method of claim 4 comprising,
between the two time-spaced depositions, etching the conductive material; and
after the second of the two time-spaced depositions, etching the conductive material prior to the cutting.

6. The method of claim 5 wherein each of the etchings is conducted without any mask being atop the substrate within the array.

7. A method of forming an array of memory cells individually comprising a capacitor and a transistor, comprising:
forming transistors over columns of data/sense lines, individual of the transistors comprising a source/drain region electrically coupled to one of the data/sense lines, the transistors comprising rows of access lines above the data/sense lines, individual of the access lines extending operatively adjacent transistor channels and interconnecting the transistors in that row;
forming elevationally-extending and longitudinally-elongated capacitor electrode lines, individual of the capacitor electrode lines being common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed longitudinally along a line of the transistors;
forming a capacitor insulator over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines;
forming an elevationally-extending conductive line over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines longitudinally along individual of the lines of transistors, individual of the conductive lines being electrically coupled to individual source/drain regions of individual transistors longitudinally along that line of transistors; and
cutting laterally through the conductive lines to form spaced individual other of the two capacitor electrodes of the individual capacitors.

8. The method of claim 7 comprising forming the source/drain region that is electrically coupled to one of the data/sense lines to be directly electrically coupled to the one of the data/sense lines.

9. The method of claim 7 comprising forming the pair of laterally-opposing sides of the capacitor electrode lines to individually to be linearly straight from top to bottom in horizontal cross section.

10. The method of claim 7 comprising forming the transistors to extend elevationally, and forming the individual access lines to comprise access line pairs that are laterally across and operatively laterally adjacent laterally-opposing sides of individual of the channels within the array.

11. The method of claim 7 comprising forming the individual capacitor electrode lines laterally to one side of the respective lines of transistors.

12. The method of claim 7 comprising:
forming the transistors to extend elevationally;
forming the source/drain region that is electrically coupled to one of the data/sense lines to be an upper source/drain region of the individual transistors and that is directly electrically coupled to the one of the data/sense lines; and
forming the individual access lines to extend laterally across and operatively laterally adjacent a lateral side of the transistor channels.

13. The method of claim 7 wherein individual of the other capacitor electrodes are formed to be directly against an uppermost surface of individual of the upper source/drain regions of the individual transistors, the individual other capacitor electrodes being directly against less than all of the respective upper source/drain region uppermost surface.

14. The method of claim 13 wherein the individual other capacitor electrodes are directly against no more than half of all of the respective upper source/drain region uppermost surface.

15. The method of claim 7 comprising forming the array within a tier of the memory cells to have translational symmetry where individual of the memory cells are 1T-1C and occupy a horizontal area of 2F 2 , where “F” is memory cell pitch taken horizontally, laterally, and orthogonally through individual of the capacitor electrode lines, the capacitor insulator, and the other capacitor electrodes.

16. The method of claim 15 comprising forming the horizontal area to be horizontally bounded by a 1F by 2F rectangle.

17. A method of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, comprising:
forming elevationally-extending lower transistors over lower columns of lower data/sense lines, individual of the lower transistors comprising a lower source/drain region directly electrically coupled to one of the lower data/sense lines, the lower transistors comprising lower rows of lower access lines above the lower data/sense lines, individual of the lower access lines extending laterally across and operatively laterally adjacent a lateral side of lower transistor channels and interconnecting the lower transistors in that lower row;
forming elevationally-extending and longitudinally-elongated capacitor electrode lines, individual of the capacitor electrode lines being common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed longitudinally along a line of the lower transistors;
forming a capacitor insulator over laterally-opposing sides longitudinally along individual of the capacitor electrode lines;
forming an elevationally-extending conductive line over the capacitor insulator longitudinally along each of a pair of laterally-opposing sides of the individual capacitor electrode lines longitudinally along individual of the lines of lower transistors, individual of the conductive lines on one of the laterally-opposing sides of the individual capacitor electrode lines being directly electrically coupled to upper source/drain regions

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal

Classifications

• H01L27/11507

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H01L28/60 Primary

  Electricity · mapped topic

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title