Memory Arrays And Methods Of Forming An Array Of Memory Cell

Patent metadata

Field	Value
Publication number	US-2016126290-A1
Application number	US-201614993306-A
Country	US
Kind code	A1
Filing date	Jan 12, 2016
Priority date	May 31, 2012
Publication date	May 5, 2016
Grant date	—

Abstract

A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

First claim

1 - 11 . (canceled)

12 . A method of forming an array of memory cells, comprising:
forming lines of covering material that are elevationally over and along lines of spaced sense line contacts; longitudinally lining void space between the lines of covering material with programmable material; depositing outer electrode material over the programmable material to over-fill remaining void space between the lines of covering material; removing the outer electrode material back at least to an elevationally outermost surface of the covering material to form lines comprising the programmable material and the outer electrode material, and to form coplanar elevationally outermost surfaces of the covering material and the outer electrode material; removing the covering material over the spaced sense line contacts and exposing the spaced sense line contacts; forming access lines; and forming sense lines that are electrically coupled to the spaced sense line contacts, the sense lines being angled relative to the lines of spaced sense line contacts and relative to the access lines.

13 . The method of claim 12 comprising also removing the programmable material back at least to the elevationally outermost surface of the covering material to form a planar outermost surface of the programmable material that is coplanar with the elevationally outermost surfaces of the covering material and the outer electrode material.

14 . The method of claim 12 comprising elevationally recessing the outer electrode material relative to the covering material after forming the coplanar elevationally outermost surfaces.

15 . The method of claim 12 wherein the removing of the covering material is of all of the covering material of the lines of covering material, and further comprising:
after removing the covering material, depositing a first dielectric to be thicker atop the lines comprising outer electrode material and programmable material than over bases between the lines comprising outer electrode material and programmable material; and
forming a second dielectric over the first dielectric to cover sidewalls of the lines comprising outer electrode material and programmable material.

16 . A method of forming an array of memory cells, comprising:
forming access lines relative to a substrate; forming lines of spaced sense line contacts between and along first pairs of the access lines and forming lines of spaced inner electrode material between and along second pairs of the access lines; forming lines of covering material that are elevationally over and along the lines of the spaced sense line contacts and between the lines of spaced inner electrode material; forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material and elevationally over and along the lines of spaced inner electrode material; removing the covering material over the spaced sense line contacts and exposing the spaced sense line contacts; and forming sense lines that are electrically coupled to the spaced sense line contacts; the sense lines being angled relative to the lines of spaced sense line contacts, the lines of programmable material and outer electrode material, and the access lines.

17 - 20 . (canceled)

21 . A method of forming an array of memory cells, comprising:
forming lines of covering material that are elevationally over and along lines of spaced sense line contacts; forming anisotropically etched dielectric sidewall spacers over sidewalls of the covering material, the dielectric spacers not containing oxygen; depositing oxygen-sensitive programmable material over the lines of covering material, the spacers, and to line void space between the spacers; depositing outer electrode material over the lines of covering material and the spacers, and over the oxygen-sensitive programmable material to over-fill remaining void space between the spacers; removing the outer electrode material back at least to an elevationally outermost surface of the covering material to form coplanar elevationally outermost surfaces of the covering material, the spacers, the oxygen-sensitive programmable material, and the outer electrode material; elevationally recessing the outermost surfaces of the oxygen-sensitive programmable material and the outer electrode material relative to the elevationally outermost surfaces of the covering material; depositing dielectric material over the outer electrode material, the oxygen-sensitive programmable material, the spacers, and the covering material; the dielectric material being of different composition from that of the covering material and not containing oxygen; removing the dielectric material back at least to an elevationally outermost surface of the covering material; etching away the lines of covering material selectively relative to the dielectric material and the dielectric spacers; depositing oxygen-containing dielectric over the dielectric material and the spacers, and to over-fill void space resulting from etching away the lines of covering material; forming access lines; etching sense line trenches into the oxygen-containing dielectric that are angled relative to the lines of spaced sense line contacts and relative to the access lines; etching individual contact openings into the oxygen-containing dielectric at bases of the sense line trenches to individual of the spaced sense line contacts; and forming conductive material within the sense line trenches and contact openings to form sense lines.

22 . The method of claim 21 wherein the elevationally recessing recesses the oxygen-sensitive programmable material more than the outer electrode material.

23 . The method of claim 21 wherein the elevationally recessing of the oxygen-sensitive programmable material and the outer electrode material occurs in a single etching step.

24 - 28 . (canceled)

29 . A memory array, comprising:
access lines and sense lines angled relative to the access lines; individual memory cells comprising an inner electrode, an outer electrode, and programmable material between the inner and outer electrodes; the outer electrode comprising an outer electrode line common to a line of individual memory cells; the outer electrode line comprising a base and opposing sidewalls; the programmable material being across the base and at least portions of each of the opposing sidewalls of individual of the outer electrode lines; and the inner electrode of individual memory cells electrically coupling to one of a pair source/drain regions on opposing sides of one of the access lines, the other of the pair of source/drain regions electrically coupling to one of the sense lines.

30 . The memory array of claim 29 wherein the programmable material is generally U-shaped in lateral cross section relative to the individual outer electrode lines.

31 . The memory array of claim 29 wherein the programmable material on at least one of the opposing sidewalls of the individual outer electrode lines has an elevationally outermost planar surface that is co-planar with a planar elevationally outermost surface of that individual outer electrode line.

32 . The memory array of claim 29 wherein the programmable material is over all of each of the opposing sidewalls of the individual outer electrode lines.

33 . The memory array of claim 29 wherein the programmable material is over only some of each of the opposing sidewalls of the individual outer electrode lines.

34 . The memory array of claim 29 wherein the programmable material compri

Assignees

• Micron Technology Inc

Inventors

• Sills Scott E
• Ramaswamy Durai Vishak Nirmal

Classifications

• H01L45/1616

  Electricity · mapped topic

• H01L45/124

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/145

  Electricity · mapped topic