Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors

Patent metadata

Field	Value
Publication number	US-10014305-B2
Application number	US-201615340838-A
Country	US
Kind code	B2
Filing date	Nov 1, 2016
Priority date	Nov 1, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally inward of the upper and lower capacitor electrode linings in the individual capacitor openings. Conductive material is formed laterally inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings. The conductive material is formed to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Additional methods and structure independent of method are disclosed.

First claim

The invention claimed is:

1. A method of forming an array comprising pairs of vertically opposed capacitors, comprising:
forming a conductive lining in individual capacitor openings in insulative-comprising material;
removing an elevational mid-portion of individual of the conductive linings to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings;
forming a capacitor insulator laterally inward of the upper and lower capacitor electrode linings in the individual capacitor openings; and
forming conductive material laterally inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors.

2. The method of claim 1 comprising forming the shared capacitor electrode to also be shared by multiple of the pairs of vertically opposed capacitors.

3. The method of claim 1 wherein the conductive lining in the individual capacitor openings comprises a container shape comprising sidewalls and a bottom extending laterally to and between the sidewalls.

4. The method of claim 1 comprising forming the conductive lining to be upwardly open.

5. The method of claim 1 comprising forming the conductive lining, the upper capacitor electrode lining, and the lower capacitor electrode lining to be totally encircling in the individual capacitor openings in horizontal cross-section.

6. The method of claim 1 comprising forming the upper capacitor electrode lining to comprise a downwardly-facing container shape comprising sidewalls and a top extending laterally to and between the sidewalls.

7. The method of claim 6 wherein the capacitor insulator is elevationally thicker between the top of the upper capacitor electrode lining and the shared capacitor electrode at its lateral center than it is laterally thick between the sidewalls of the upper capacitor electrode lining and the shared capacitor electrode.

8. The method of claim 1 wherein the removing comprises etching the elevational mid-portion of the conductive linings starting from a laterally-outer side of the elevational mid-portions of the conductive linings.

9. The method of claim 1 wherein the removing comprises etching the elevational mid-portion of the conductive linings starting from a laterally-inner side of the elevational mid-portions of the conductive linings.

10. The method of claim 1 wherein, during the removing, covering material is over at least a majority of laterally-internal sidewalls of the conductive linings except for laterally-internal sidewalls of the mid-portions during the removing.

11. The method of claim 10 comprising removing all remaining of said covering material prior to forming the conductive material of the shared capacitor electrode.

12. The method of claim 1 wherein the capacitor insulator comprises programmable material such that the capacitors are non-volatile and programmable into at least two different magnitude capacitive states.

13. The method of claim 1 wherein the capacitor insulator comprises dielectric material such that the capacitors are volatile.

14. The method of claim 1 wherein the insulative-comprising material comprises an upper insulative material, a lower insulative material, and sacrificial material elevationally there-between; and
further comprising:
removing the sacrificial material to form a void space elevationally between the upper and lower insulative materials laterally between the individual capacitor openings and into which the capacitor insulator and the conductive material are formed.

15. The method of claim 14 wherein the sacrificial material is not dielectric.

16. The method of claim 15 wherein the sacrificial material is predominately elemental-form silicon.

17. The method of claim 14 wherein the sacrificial material is dielectric.

18. The method of claim 14 comprising removing the sacrificial material to form the void space before removing the elevational mid-portions of the individual conductive linings.

19. The method of claim 14 comprising removing the sacrificial material to form the void space after removing the elevational mid-portions of the individual conductive linings.

20. The method of claim 1 wherein the capacitor insulator is directly against all top and bottom surfaces of the shared capacitor electrode.

21. The method of claim 20 wherein the capacitor insulator is directly against all sidewall edge surfaces of the shared capacitor electrode.

22. The method of claim 1 comprising forming the vertically opposed capacitors to individually comprise part of an individual memory cell.

23. The method of claim 22 comprising:
forming transistors that ultimately are below the lower capacitor electrode linings that individually have a source/drain region thereof electrically coupled to individual of the lower capacitor electrode linings; and
forming transistors that ultimately are above the upper capacitor electrode linings that individually have a source/drain region thereof electrically coupled to individual of the upper capacitor electrode linings.

24. The method of claim 23 comprising:
forming the transistors that are below the lower capacitor electrode linings to be lower elevationally-extending transistors, the source/drain region of the respective lower elevationally-extending transistor being electrically coupled to individual of the lower capacitor electrode linings; and
forming the transistors that are above the upper capacitor electrode linings to be upper elevationally-extending transistors, the source/drain region of the respective upper elevationally-extending transistor being electrically coupled to individual of the upper capacitor electrode linings.

25. The method of claim 24 comprising forming the upper and lower elevationally-extending transistors to be vertical transistors.

26. A method of forming an array comprising pairs of vertically opposed capacitors, comprising:
forming an upwardly-open conductive lining in individual capacitor openings, the capacitor openings extending through upper insulative material, into lower insulative material, and through sacrificial material elevationally there-between to a node location and to which individual of the conductive linings in the individual capacitor openings electrically couple;
forming covering material over laterally-internal sidewalls of the conductive linings in the individual capacitor openings, the covering material covering at least a majority of those laterally-internal sidewalls that are laterally over each of the upper insulative material and the lower insulative material;
after forming the covering material, removing both of the sacrificial material and an elevational mid-portion of the individual conductive linings that is elevationally between the upper and lower insulative materials in the individual capacitor openings, the removing being conducted selectively relative to the covering material and the upper and lower insulative materials, the removing of the sacrificial material forming a void space elevationally between the upper and lower insulative materials laterally between the individual capacitor openings, an upper portion of the individual capacitor opening

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal

Classifications

• H01L27/11507 Primary

  Electricity · mapped topic

• H01L28/60

  Electricity · mapped topic

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title