Semiconductor device and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9287270-B2
Application number	US-201414279301-A
Country	US
Kind code	B2
Filing date	May 15, 2014
Priority date	Oct 2, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a plurality of lower electrodes formed on the substrate, wherein:
each lower electrode extends vertically upward away from the substrate,
first lower electrodes of the plurality of lower electrodes include a bottom cylinder portion at a first height that has vertical walls on all sides and a top cylinder portion at a second height above the first height that also has vertical walls on all sides, and
second lower electrodes of the plurality of lower electrodes include a bottom cylinder portion at the first height that has vertical walls on all sides and a top cylinder portion at the second height that has vertical walls on at least one side but no walls on at least part of the top cylinder portion;
a dielectric layer formed on the plurality of lower electrodes; and
an upper electrode formed on the plurality of lower electrodes and on the dielectric layer, wherein:
the upper electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer,
the first semiconductor compound layer is formed above portions of the second lower electrodes having no walls on at least part of the top cylinder portion and is not formed above the first lower electrodes; and
the first semiconductor compound layer is formed between the second lower electrodes and the second semiconductor compound layer.

2. The semiconductor device of claim 1 , wherein:
the upper electrode further comprises a portion that includes a metal and is disposed to contact the dielectric layer.

3. The semiconductor device of claim 1 , wherein:
the crystallinity of the first semiconductor compound layer is lower than that of the second semiconductor compound layer.

4. The semiconductor device of claim 1 , wherein:
the lower electrodes and the upper electrode form capacitor electrodes in a semiconductor memory device.

5. A semiconductor device comprising:
first storage electrodes and second storage electrodes adjacent to each other and each having a cylinder shape;
a supporter pattern between the first storage electrodes and the second storage electrodes;
a dielectric film on the first storage electrodes and the second storage electrodes;
a recess on a portion of a sidewall of each of the first storage electrodes; and
an upper electrode formed on the dielectric film,
wherein the upper electrode includes a first semiconductor compound layer formed in the recess and a second semiconductor compound layer formed on the first semiconductor compound layer, and the first semiconductor compound layer and the second semiconductor compound layer have different compositions.

6. The semiconductor device of claim 5 , wherein the first semiconductor compound layer and the second semiconductor compound layer include SiGe, and the Si concentration of the first semiconductor compound layer is higher than that of the second semiconductor compound layer.

7. The semiconductor device of claim 5 , wherein the crystallinity of the first semiconductor compound layer is lower than that of the second semiconductor compound layer.

8. The semiconductor device of claim 5 , wherein the supporter pattern contacts the first storage electrodes and the second storage electrodes.

9. The semiconductor device of claim 8 , wherein the dielectric film is conformally formed along top surfaces and sidewalls of the first storage electrodes, a top surface of the supporter pattern and sidewalls and top surfaces of the second storage electrodes.

10. The semiconductor device of claim 9 , wherein the upper electrode further includes a metal portion, the metal portion is formed in contact with the dielectric film and fills spaces between the sidewalls of the first storage electrodes and the sidewalls of the second storage electrodes.

11. The semiconductor device of claim 9 , wherein a thickness of the dielectric film formed on the top surface of each of the second storage electrodes is greater than that of the dielectric film formed on the sidewalls of the second storage electrodes.

12. A semiconductor device comprising:
a storage electrode having a cylinder shape;
a dielectric film on the storage electrode; and
a plate electrode on the dielectric film,
wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer,
wherein a recess is formed on a first sidewall of the storage electrode and a recess is not formed on a second sidewall of the storage electrode, and the first semiconductor compound layer is formed in the recess above the first sidewall and is not formed above the second sidewall.

13. The semiconductor device of claim 12 , wherein the crystallinity of the first semiconductor compound layer is lower than that of the second semiconductor compound layer.

14. The semiconductor device of claim 12 , wherein the first semiconductor compound layer and the second semiconductor compound layer include a plurality of semiconductor elements, which are the same as each other, the first semiconductor compound layer and the second semiconductor compound layer having different composition ratios of those semiconductor elements.

15. The semiconductor device of claim 12 , wherein the first semiconductor compound layer and the second semiconductor compound layer include SiGe, and the first semiconductor compound layer has a higher Si concentration than the second semiconductor compound layer.

16. The semiconductor device of claim 12 , wherein the plate electrode further includes a metal film that contacts the dielectric film.

17. The semiconductor device of claim 12 , wherein a metal film, a first semiconductor compound layer that contacts the metal film, and a second compound that contacts the first semiconductor compound layer are formed on the first sidewall, and a metal film and a second semiconductor compound layer that contacts the metal film are formed on the second sidewall.

18. The semiconductor device of claim 12 , further comprising a supporter pattern formed at the second sidewall.

19. The semiconductor device of claim 5 , wherein the first semiconductor compound layer of the upper electrode is not formed on the second storage electrodes.

20. The semiconductor device of claim 12 , wherein the second semiconductor compound is formed above the first semiconductor compound formed in the recess, and extends in a direction perpendicular to the direction in which the first and second semiconductor compounds are stacked.

Assignees

• Oh Jung-Hwan
• Kim Hyun-Jun
• Seo Jong-Bom
• Im Ki-Vin
• Lim Han-Jin
• Samsung Electronics Co Ltd

Inventors

• Oh Jung-Hwan
• Kim Hyun-Jun
• Seo Jong-Bom
• Im Ki-Vin
• Lim Han-Jin

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/31 Primary

  having a storage electrode stacked over the transistor · CPC title

• H01L27/10808

  Electricity · mapped topic