Devices and methods of forming higher tunability FinFET varactor

Patent metadata

Field	Value
Publication number	US-9437713-B2
Application number	US-201414181790-A
Country	US
Kind code	B2
Filing date	Feb 17, 2014
Priority date	Feb 17, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

First claim

What is claimed is:

1. A method comprising:
obtaining an intermediate semiconductor device, comprising:
a substrate;
a dielectric layer over the substrate; and
a plurality of mandrels formed on the dielectric layer;

applying a spacer layer over the intermediate semiconductor device;
etching the intermediate semiconductor device to remove a horizontal portion of the spacer layer to form at least one vertical portion of the spacer layer and to expose a top surface of the plurality of mandrels, the at least one vertical portion of the spacer layer comprising:
a first set of spacers with a first width; and
a second set of spacers with a second width, wherein the first width is about twice the size as the second width;

removing the plurality of mandrels;
etching the intermediate semiconductor device to remove at least a portion of the dielectric layer to form a first set of masks under the first set of spacers and a second set of masks under the second set of spacers;
forming at least one first fin and at least one second fin, wherein the intermediate semiconductor device now comprises:
a portion of the substrate;
the at least one first fin extending above the portion of the substrate, the at least one first fin having a first fin width;
the at least one second fin extending above the portion of the substrate, the at least one second fin having a second fin width and wherein the first fin width is about twice the size of the second fin width;
the first set of masks positioned on the at least one first fin;
the second set of masks positioned on the at least one second fin;
the first set of spacers positioned on the first set of masks; and
the second set of spacers positioned on the second set of masks; and

removing the at least one vertical portion of the spacer layer and the dielectric layer.

2. The method of claim 1 , wherein the first set of spacers remaining after removing the plurality of mandrels is a double spacer.

3. The method of claim 2 , wherein the double spacer has a width ranging from about 10 nm to about 20 nm for a 20 nm technology node.

4. The method of claim 1 , wherein the at least one fin has a double fin width.

5. The method of claim 4 , wherein the double fin width ranges from about 10 nm to about 40 nm.

6. The method of claim 1 , further comprising:
forming a gate over the at least one fin.

7. The method of claim 6 , further comprising:
forming at least one contact over the gate; and
forming at least one contact over the at least one fin.

8. The method of claim 1 , further comprising:
doping the at least one fin.

9. The method of claim 8 , wherein doping the at least one fin comprises:
implanting n+ into the at least one fin.

10. The method of claim 8 , wherein doping the at least one fin comprises:
implanting p+ into the at least one fin.

11. The method of claim 1 , wherein the at least one first fin comprises:
a bottom portion adjacent to the portion of the substrate; and
a top portion on top of the bottom portion, wherein a width of the at least one first fin gradually increases from the top portion to the bottom portion; and
wherein the at least one second fin comprises:
a bottom portion adjacent to the portion of the substrate; and
a top portion on top of the bottom portion, wherein a width of the at least one second fin gradually increases from the top portion to the bottom portion.

Assignees

• Globalfoundries Inc

Inventors

• Singh Jagar
• Wei Andy
• Srinivasan Gopal
• Gendron Amaury

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title