Structure and method for FinFET SRAM

Patent metadata

Field	Value
Publication number	US-9673202-B2
Application number	US-201614991526-A
Country	US
Kind code	B2
Filing date	Jan 8, 2016
Priority date	Feb 27, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure.

First claim

What is claimed is:

1. An integrated circuit (IC) layout, comprising:
at least four first patterns located at a first layer of the IC layout, wherein the first patterns are spaced from each other in a first direction; and each of the first patterns is an elongated shape extending lengthwise in a second direction that is orthogonal to the first direction;
at least four second patterns located at a second layer of the IC layout, wherein each of the second patterns is an elongated shape extending lengthwise in the second direction, the second patterns are spaced from each other in the first direction, each of the second patterns covers a side of one of the first patterns when the first and second layers are superimposed, the side extending in the second direction; and
third patterns located at a third layer of the IC layout, wherein the third patterns are spaced from each other, each of the third patterns covers a portion of another side of one of the first patterns that is not covered by the second patterns when the first, second, and third layers are superimposed, the another side extending in the second direction,
wherein:
the first, second, and third patterns are used for collectively defining active regions for forming transistors; and
the active regions are defined along sides of the first patterns that extend in the second direction and are not covered by the second and third patterns when the first, second, and third layers are superimposed.

2. The IC layout of claim 1 , wherein each of the third patterns partially overlaps with two of the second patterns when the second and third layers are superimposed.

3. The IC layout of claim 1 , wherein the first patterns define mandrels in a mandrel-spacer patterning process for forming spacers, and the second and third patterns define cut patterns for at least partially removing the spacers.

4. The IC layout of claim 1 , further comprising:
gate features located at a gate layer of the IC layout,
wherein each of the gate features is an elongated shape extending lengthwise in the first direction; the gate features are spaced from each other in the second direction by a gate pitch; some of the gate features are used for forming P-transistors with respective ones of the active regions; and some of the gate features are used for forming N-transistors with respective ones of the active regions.

5. The IC layout of claim 4 , wherein the gate features and the active regions are to form at least twelve transistors and the at least twelve transistors are to form at least two SRAM cells.

6. The IC layout of claim 1 , wherein the number of the first patterns equals to the number of the second patterns.

7. The IC layout of claim 1 , wherein the number of the first patterns is greater than the number of the second patterns.

8. A semiconductor device comprising:
a first plurality of first SRAM cells, wherein the first plurality is arranged to have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction, the first plurality includes FinFET transistors formed by first gate features and first fin active lines;
a second plurality of peripheral logic circuits, wherein the second plurality includes FinFET transistors formed by second gate features and second fin active lines, the second gate features are arranged to have a third pitch in the second direction, and the second fin active lines are arranged to have a fourth pitch in the first direction; and
a third plurality of second SRAM cells, wherein the third plurality is arranged to have a fifth pitch in the first direction and a sixth pitch in the second direction, the third plurality includes FinFET transistors formed by third gate features and third fin active lines,
wherein:
the second SRAM cells are different from the first SRAM cells;
the second pitch is about twice of the third pitch; and
the sixth pitch is about the same as the second pitch.

9. The semiconductor device of claim 8 , wherein the second SRAM cell has more fin active lines than the first SRAM cell.

10. The semiconductor device of claim 8 , wherein the first SRAM cell has one access port, and the second SRAM cell has two access ports.

11. The semiconductor device of claim 8 , wherein a ratio between the first pitch and the fourth pitch is about one of: 8, 8.5, 9, 10, 10.5, and 11.

12. The semiconductor device of claim 8 , wherein a ratio between the first pitch and the second pitch is in a range from 2.25 to 2.28, wherein another ratio between the fifth pitch and the sixth pitch is in a range from 2.7 to 2.9.

13. The semiconductor device of claim 8 , wherein a ratio between the first pitch and the fourth pitch is not an integer, and another ratio between the fifth pitch and the fourth pitch is an integer.

14. The semiconductor device of claim 8 , wherein the fifth pitch is greater than the first pitch by about twice of the fourth pitch.

15. A mask set for semiconductor lithography process, comprising:
a first mask having at least four first patterns, wherein the first patterns are spaced from each other in a first direction, and each of the first patterns is an elongated shape extending lengthwise in a second direction that is orthogonal to the first direction;
a second mask having at least four second patterns, wherein each of the second patterns is an elongated shape extending lengthwise in the second direction, the second patterns are spaced from each other in the first direction, and each of the second patterns covers a side of one of the first patterns when the first and second masks are superimposed, the side extending in the second direction; and
a third mask having third patterns, wherein the third patterns are spaced from each other, and each of the third patterns covers a portion of another side of one of the first patterns that is not covered by the second patterns when the first, second, and third masks are superimposed, the another side extending in the second direction,
wherein:
the first patterns define mandrels in a mandrel-spacer patterning process for forming spacers; and
the second and third patterns define cut patterns for at least partially removing the spacers.

16. The mask set of claim 15 , wherein each of the third patterns partially overlaps with two of the second patterns when the second and third masks are superimposed.

17. The mask set of claim 15 , further comprising:
a fourth mask having fourth patterns,
wherein each of the fourth patterns is an elongated shape extending lengthwise in the first direction, and the fourth patterns are spaced from each other in the second direction; and
wherein the first, second, and third patterns collectively define fin active lines for FinFET type of transistors, and the fourth patterns define gate features for the FinFET type of transistors.

18. The mask set of claim 15 , wherein the number of the first patterns in the first mask equals to the number of the second patterns in the second mask.

19. The mask set of claim 15 , wherein the number of the first patterns in the first mask is greater than the number of the second patterns in the second mask.

20. The mask set of claim 15 , wherein the first mask includes at least eight first patterns, and the second mask includes at least eight second patterns.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title