Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9607985-B1
Application number	US-201514864908-A
Country	US
Kind code	B1
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a base;
a plurality of fin shaped structures protruded from the base, wherein each of the fin shaped structures has a width;
a first trench, recessed from the base of the substrate and having a depth being smaller than a width of each of the fin shaped structures, wherein a width of the first trench is at least greater than two times of the width of the fin shaped structures;
at least one bump only disposed on a surface of the first trench, wherein the at least one bump is lower than the base and is higher than a bottom surface of the first trench; and
a second trench, recessed from the base of the substrate and having a depth being smaller than the width of each of the fin shaped structures.

2. The semiconductor device according to claim 1 , wherein a width of the second trench is substantially equal to the width of each of the fin shaped structures.

3. The semiconductor device according to claim 1 , further comprising:
a shallow trench isolation surrounding the fin shaped structures.

4. The semiconductor device according to claim 3 , wherein the shallow trench isolation further comprises at least two protruding portions in the first trench, and the at least one bump is disposed between the at least two protruding portions.

5. The semiconductor device according to claim 4 , wherein a number of the at least two protruding portions is x and a number of the at least one bump is x−1.

6. The semiconductor device according to claim 1 , wherein the at least one bump has a smooth rounding surface.

7. The semiconductor device according to claim 1 , wherein the at least one bump has an angle to the surface of the first trench, and the angle is greater than 90 degrees.

8. The semiconductor device according to claim 1 , further comprising:
a tip portion protruding from the base, wherein the tip portion is disposed between the first trench and the fin shaped structures.

9. The semiconductor device according to claim 1 , wherein the tip portion is substantially between 1-10 angstrom.

10. The semiconductor device according to claim 1 , wherein the at least one bump has a same pitch as a pitch of the fin shaped structures.

11. A method of forming a semiconductor device, comprising:
providing a substrate having a base and a plurality of fin shaped structures formed on the base, wherein the substrate has a first region and a second region and each of the fin shaped structures has a width;
forming an organic dielectric layer entirely covering the substrate and the fin shaped structures;
partially removing the organic dielectric layer disposed in the second region;
partially removing the fin shaped structures disposed in the second region; and
further removing the fin shaped structures disposed in the second region, to form a first trench and a least one bump, wherein the first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures, and a width of the first trench is at least greater than two times of the width of the fin shaped structures, and the at least one bump is higher than a bottom surface of the first trench.

12. The method of forming a semiconductor device of claim 11 , wherein the at least one bump is formed between any two of the removed fin shaped structures in the second region.

13. The method of forming a semiconductor device of claim 11 , further comprising:
forming a shallow trench isolation surrounding the fin shaped structures.

14. The method of forming a semiconductor device of claim 13 , wherein the shallow trench isolation further comprises at least two protruding portions in the first trench, and a number of the at least two protruding portions is x and a number of the at least one bump is x−1.

15. The method of forming a semiconductor device of claim 11 , wherein the substrate further comprises a third region and the method further comprising:
partially removing the fin shaped structures disposed in the third region while the fin shaped structures in the second region are partially removed; and
further removing the fin shaped structures disposed in the third region while the fin shaped structures in the second region are further removed, to form a second trench, wherein a width of the second trench is substantially equal to the width of each of the fin shaped structures.

16. The method of forming a semiconductor device of claim 15 , wherein the second trench does not have any bump disposed thereon.

17. The method of forming a semiconductor device of claim 11 , wherein when partially removing of the fin shaped structures, an etching selectivity between the fin shaped structures relative to the organic dielectric layer is substantially greater than 1.

18. The method of forming a semiconductor device of claim 11 , wherein when further removing of the fin shaped structures, an etching selectivity between the fin shaped structures relative to the organic dielectric layer is substantially greater than 1.

Assignees

• United Microelectronics Corp

Inventors

• Tseng I-Ming
• Liang Wen-An
• Huang Chen-Ming

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title