Method of forming pattern of semiconductor device

US2017148643A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017148643-A1
Application numberUS-201615355360-A
CountryUS
Kind codeA1
Filing dateNov 18, 2016
Priority dateNov 19, 2015
Publication dateMay 25, 2017
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to the first distance and being spaced apart from an adjacent unit by a second distance equal to the first width, forming a spacer conformally covering the first and second units, the spacer having a first thickness and being merged between the second units, removing a portion of the spacer on upper surfaces of the first and second units, and etching the mask in a region from which first and second units have been removed.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of forming a pattern of a semiconductor device, the method comprising: sequentially forming a mask layer and a sacrificial layer on a substrate that includes a first area and a second area; etching the sacrificial layer in the first area of the substrate to form a plurality of first sacrificial pattern units, each first sacrificial pattern unit having a first width and being spaced apart from an adjacent first sacrificial pattern unit by a first distance; etching the sacrificial layer in the second area of the substrate to form a plurality of second sacrificial pattern units, each second sacrificial pattern unit having a second width equal to the first distance and being spaced apart from an adjacent first sacrificial pattern unit by a second distance equal to the first width; forming a spacer film conformally covering the plurality of first sacrificial pattern units and the plurality of second sacrificial pattern units, the spacer film having a first thickness and being merged between the plurality of second sacrificial pattern units; removing a portion of the spacer film covering upper surfaces of the plurality of first sacrificial pattern units and of the plurality of second sacrificial pattern units to expose the upper surfaces of the plurality of first sacrificial pattern units and the plurality of second sacrificial pattern units; removing the plurality of first and second sacrificial pattern units; and etching the mask layer in a region in which the plurality of first sacrificial pattern units and the plurality of second sacrificial pattern units are removed, so as to form a mask pattern. 2 . The method as claimed in claim 1 , wherein the first width is smaller than the second width, and the first distance is larger than the second distance. 3 . The method as claimed in claim 2 , wherein the first distance is more than two times the first thickness, and the second distance is two or less times the first thickness. 4 . The method as claimed in claim 1 , further comprising: forming a photoresist layer on the sacrificial layer; exposing and developing the photoresist layer in the first area using a first photo mask to form a plurality of first photoresist pattern units; and exposing and developing the photoresist layer in the second area using a second photo mask to form a plurality of second photoresist pattern units, wherein the first photo mask and the second photo mask are phase-inverted to each other. 5 . The method as claimed in claim 1 , further comprising removing the spacer film not disposed between the plurality of second sacrificial pattern units, after forming the spacer film. 6 . The method as claimed in claim 1 , wherein exposing the upper surfaces of the plurality of first and second sacrificial pattern units includes: forming a first spacer in the first area; and forming a second spacer in the second area, the width of the second spacer being two times the width of the first spacer. 7 . The method as claimed in claim 6 , wherein forming the mask pattern includes etching the mask layer using the first spacer and the second spacer as a mask. 8 . The method as claimed in claim 7 , further comprising: forming an interlayer insulating film covering the mask pattern; and removing the mask pattern to form a trench. 9 . The method as claimed in claim 1 , wherein the first area is a cell area, and the second area is a scribe lane area. 10 . The method as claimed in claim 9 , further comprising forming an overlay key using the mask pattern in the second area, after forming the mask pattern. 11 . A method of forming a pattern of a semiconductor device, the method comprising: sequentially forming a mask layer, a sacrificial layer, and a photoresist layer on a substrate that includes a first area and a second area; exposing and developing the photoresist layer in the first area of the substrate using a first photo mask to form a plurality of first photoresist pattern units; and exposing and developing the photoresist layer in the second area of the substrate using a second photo mask to form a plurality of second photoresist pattern units; etching the sacrificial layer using the plurality of first photoresist pattern units and the plurality of second photoresist pattern units to respectively form a plurality of first sacrificial pattern units and a plurality of second sacrificial pattern units in the first area and the second area; forming a spacer film conformally covering the plurality of first sacrificial pattern units and the plurality of second sacrificial pattern units, the spacer film having a first thickness and being merged between the plurality of second sacrificial pattern units; removing the spacer film covering upper surfaces of the plurality of first sacrificial pattern units and upper surfaces of the plurality of second sacrificial pattern units to expose the upper surfaces of the plurality of first sacrificial pattern units and the upper surfaces of the plurality of second sacrificial pattern units; removing the plurality of first and second sacrificial pattern units; and etching the mask layer disposed in a region in which the plurality of first sacrificial pattern units and the plurality of second sacrificial pattern units are removed, so as to form a mask pattern, wherein each of the plurality of first photoresist pattern units has a first width and the plurality of first photoresist pattern units are spaced apart from each other by a first distance, and each of the plurality of second photoresist pattern units has a second width and the plurality of second photoresist pattern units are spaced apart from each other by a second distance, and wherein the first width is smaller than the second width, and the first distance is larger than the second distance. 12 . The method as claimed in claim 11 , wherein the first distance is more than two times the first thickness, and the second distance is two or less times the first thickness. 13 . The method as claimed in claim 11 , further comprising removing the spacer film not disposed between the plurality of second sacrificial pattern units, after forming the spacer film. 14 . The method as claimed in claim 11 , wherein exposing the upper surfaces of the plurality of first sacrificial pattern units and the upper surfaces of the plurality of second sacrificial pattern units includes: forming a first spacer in the first area; and forming a second spacer in the second area, the width of the second spacer being two times the width of the first spacer. 15 . The method as claimed in claim 14 , wherein forming the mask pattern includes etching the mask layer using the first spacer and the second spacer as a mask. 16 . A method of forming a pattern of a semiconductor device, the method comprising: sequentially forming a mask layer and a sacrificial layer on a substrate; etching the sacrificial layer in a first area of the substrate to form a plurality of first sacrificial pattern units, each first sacrificial pattern unit having a first width and being spaced apart from an adjacent first sacrificial pattern unit by a first distance; etching the sacrificial layer in a second area of the substrate to form a plurality of second sacrificial pattern units, each second sacrificial pattern unit having a second width equal to the first distance and being spaced apart from an adjacent second sacrificial pattern unit by a second distance equal to the first width; conformally forming a spacer film on the plurality of first and second sacrificial pat

Assignees

Inventors

Classifications

  • characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

  • Located in scribe lines · CPC title

  • for alignment · CPC title

  • Marks applied to devices, e.g. for alignment or identification · CPC title

  • characterised by the processes involved to create the masks · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2017148643A1 cover?
A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to t…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P76/4085. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu May 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).