Multi-chip package and method of providing die-to-die interconnects in same

Patent metadata

Field	Value
Publication number	US-10510669-B2
Application number	US-201815876080-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Jun 24, 2009
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

First claim

What is claimed is:

1. A multi-chip package comprising:
a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side, the third side constituting a portion of an outside perimeter of the substrate;
a first die attached to the first side of the substrate and a second die attached to the first side of the substrate;
a bridge within an opening of the substrate, the bridge attached to the first die and to the second die, wherein the bridge creates a connection between the first die and the second die; and
one or more wire bonds coupling the bridge die to the substrate.

2. The multi-chip package of claim 1 , wherein the bridge comprises silicon.

3. The multi-chip package of claim 1 , wherein the opening of the substrate completely laterally surrounds the bridge.

4. The multi-chip package of claim 1 , wherein the bridge has an exposed backside opposite the first die and the second die.

5. The multi-chip package of claim 1 , wherein portions of the first die and second die overhanging the bridge have interconnect structures a smaller pitch than interconnect structures of portions of the first die and second die not overhanging the bridge.

6. The multi-chip package of claim 1 , wherein the first die and the second die are flip chip or controlled collapse attached to the bridge.

7. The multi-chip package of claim 1 , wherein the bridge does not include a through silicon via.

Assignees

• Intel Corp

Inventors

• Braunisch Henning
• Chiu Chia-Pin
• Aleksov Aleksandar
• Au Hinmeng
• Lotz Stefanie M
• Swan Johanna M
• Sharan Sujit

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title