Chip package structure and chip package structure array

Patent metadata

Field	Value
Publication number	US-10504847-B2
Application number	US-201715842822-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Nov 9, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.

First claim

What is claimed is:

1. A chip package structure, comprising:
a plurality of first chips, each of the first chips having a first active surface;
a plurality of first conductive pillars, each of the first conductive pillars being disposed on the first active surface of the corresponding first chip;
a second chip, having a second active surface, and the second chip is an one-side connect die;
a plurality of second conductive pillars, each of the second conductive pillars is connected between the first active surface of the corresponding first chip and the second active surface of the corresponding second chip, the second chip is electrically connected to the first active surfaces of the first chips only through the second conductive pillars, and a height of the first conductive pillars with respect to the first active surface is larger than a height of the second chip and the second conductive pillars with respect to the first active surface;
an encapsulated material, covering the first chips, the second chip and the second conductive pillars, and partially covering the first conductive pillars; and
a redistribution structure, disposed on the encapsulated material and connecting with the first conductive pillars, wherein a part of the encapsulated material is located between the second chip and the redistribution structure.

2. The chip package structure as recited in claim 1 , wherein a distribution density of the second conductive pillars is greater than a distribution density of the first conductive pillars.

3. The chip package structure as recited in claim 1 , wherein an orthographic projection area of the second conductive pillars on the first chips is less than or equal to an orthographic projection area of the first conductive pillars on the first chips.

4. The chip package structure as recited in claim 1 , wherein a height of the second conductive pillars with respect to the first active surface is less than or equal to a height of the first conductive pillars with respect to the first active surface.

5. The chip package structure as recited in claim 1 , wherein the first chips are electrically connected to each other through the redistribution structure.

6. The chip package structure as recited in claim 1 , further comprising:
a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips and the encapsulated material are disposed on the carrier.

7. The chip package structure as recited in claim 1 , further comprising:
a supporting structure, surrounding the first chips and embedded in the encapsulated material, and a part of the encapsulated material is located between the supporting structure and the redistribution structure.

8. The chip package structure as recited in claim 7 , wherein the supporting structure is exposed at one side of the encapsulated material.

9. The chip package structure as recited in claim 7 , further comprising:
a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips, the encapsulated material and the supporting structure are disposed on the carrier.

10. The chip package structure as recited in claim 9 , wherein the supporting structure is exposed at one side of the encapsulated material and one side of the carder.

11. The chip package structure as recited in claim 1 , wherein the redistribution structure comprises a plurality of patterned conductive layers, a plurality of dielectric layers, and a plurality of conductive vias, wherein the plurality of dielectric layers and the patterned conductive layers are alternately stacked to one another, and each of the conductive vias is located in the corresponding dielectric layer and electrically connected to the corresponding patterned conductive layers.

12. The chip package structure as recited in claim 1 , further comprising:
a plurality of conductive contacts, wherein the redistribution structure has a plurality of redistribution pads, and the conductive contacts are respectively disposed on the redistribution pads.

13. A chip package structure array, comprising:
a plurality of chip package structures, adapted to be arranged in array and form the chip package structure array, each of the chip package structures comprises:
a plurality of first chips, each of the first chips having a first active surface;
a plurality of first conductive pillars, each of the first conductive pillars being disposed on the first active surface of the corresponding first chip;
a second chip, having a second active surface, and the second chip is an one-side connect die;
a plurality of second conductive pillars, each of the second conductive pillars is connected between the first active surface of the corresponding first chip and the second active surface of the corresponding second chip, the second chip is electrically connected to the first active surfaces of the first chips only through the second conductive pillars, and a height of the first conductive pillars with respect to the first active surface is larger than a height of the second chip and the second conductive pillars with respect to the first active surface;
an encapsulated material, covering the first chips, the second chip and the second conductive pillars, and partially covering the first conductive pillars; and
a redistribution structure, disposed on the encapsulated material and connecting with the first conductive pillars, wherein a part of the encapsulated material is located between the second chip and the redistribution structure.

14. The chip package structure array as recited in claim 13 , wherein a distribution density of the second conductive pillars is greater than a distribution density of the first conductive pillars.

15. The chip package structure array as recited in claim 13 , wherein an orthographic projection area of the second conductive pillars on the first chips is less than or equal to an orthographic projection area of the first conductive pillars on the first chips.

16. The chip package structure array as recited in claim 13 , wherein a height of the second conductive pillars with respect to the first active surface is less than or equal to a height of the first conductive pillars with respect to the first active surface.

17. The chip package structure array as recited in claim 13 , wherein the first chips are electrically connected to each other through the redistribution structure.

18. The chip package structure array as recited in claim 13 , wherein the chip package structure further comprises:
a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips and the encapsulated material are disposed on the carrier.

19. The chip package structure array as recited in claim 13 , wherein the chip package structure further comprises:
a supporting structure, surrounding the first chips and embedded in the encapsulated material, and a part of the encapsulated material is located between the supporting structure and the redistribution structure.

20. The chip package structure array as recited in claim 19 , wherein the chip package structure further comprises:
a carrier, wherein the carrier is made of a heat dissipation material and serves as a heat dissipation element, and the first chips, the encapsulated material and the supporting structure are disposed on the carrier.

21. The chip package structure array as recited in claim

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Chang Wen-Yuan
• Hsu Yeh-Chi
• Lu Hsueh-Chung Shelton
• Chen Wei-Cheng

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/853

  On the same surface · CPC title