Semiconductor package and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9761559-B1
Application number	US-201615135539-A
Country	US
Kind code	B1
Filing date	Apr 21, 2016
Priority date	Apr 21, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both the first logic die and the second logic die, a redistribution layer (RDL) structure coupled to the first logic die and the second logic die, and a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die. The first logic die and the second logic die are coplanar.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first logic die;
a second logic die located laterally adjacent to the first logic die, a first active face of the first logic die and a second active face of the second logic die facing a same direction;
a bridge memory die coupled to both the first logic die and the second logic die on a first inactive face of the first logic die and a second inactive face of the second logic die opposite the first active face and the second active face;
a redistribution layer (RDL) structure coupled to the first logic die and the second logic die, wherein the bridge memory die is electrically coupled to the RDL structure through a plurality of through substrate vias extending from the first inactive face, through the first logic die, to the first active face and from the second inactive face, through the second logic die, to the second active face; and
a molding compound at least partially encapsulating the first logic die, the second logic, and the bridge memory die.

2. The semiconductor package according to claim 1 , wherein the first active face of the first logic die and the second active face of the second logic die are coplanar.

3. The semiconductor package according to claim 1 , wherein the bridge memory die is electrically coupled to the first logic die and the second logic die in a face-to-face configuration, such that an active surface of the bridge memory die faces the first inactive face and the second inactive face.

4. The semiconductor package according to claim 1 , wherein the bridge memory die is a dual-port RAM.

5. The semiconductor package according to claim 1 , wherein the bridge memory die is a dual-port DRAM.

6. The semiconductor package according to claim 1 , wherein the first logic die comprises central processing units, graphics processing units, or application processors.

7. The semiconductor package according to claim 1 , wherein the second logic die comprises central processing units, graphics processing units, or application processors.

8. The semiconductor package according to claim 1 , wherein the bridge memory die allows inter-processor communication between the first logic die and the second logic die.

9. The semiconductor package according to claim 1 , wherein the first logic die is electrically coupled to the RDL structure through a plurality of first connecting elements.

10. The semiconductor package according to claim 9 , wherein the second logic die is electrically coupled to the RDL structure through a plurality of second connecting elements.

11. The semiconductor package according to claim 10 , wherein the bridge memory die is electrically coupled to the first logic die and the second logic die through a plurality of third connecting elements.

12. The semiconductor package according to claim 11 , wherein the first connecting elements, the second connecting elements, and the third connecting elements comprise metal bumps or metal pillars.

13. The semiconductor package according to claim 1 , wherein the first logic die and the second logic die are interposed between the RDL structure and the bridge memory die.

14. The semiconductor package according to claim 13 , further comprising an upper redistribution layer structure on the bridge memory die and on the molding compound, and at least a through mold via in the molding compound electrically connected to the upper redistribution layer structure.

15. The semiconductor package according to claim 14 , wherein the through mold via is electrically connected to the RDL structure.

16. The semiconductor package according to claim 14 , wherein the bridge memory die comprises through substrate vias electrically connected to the upper redistribution layer structure.

17. The semiconductor package according to claim 1 , further comprising a plurality of solder bumps or solder balls mounted on a lower surface of the RDL structure.

Assignees

• Micron Technology Inc

Inventors

• Shih Shing-Yih
• Wu Tieh-Chiang

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/072

  of bump connectors · CPC title