Semiconductor device with via bar

Patent metadata

Field	Value
Publication number	US-9263370-B2
Application number	US-201314040223-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A semiconductor device comprising a second surface of a logic die and a second surface of a via bar coupled to a first surface of a substrate, a second surface of a memory die coupled to a first surface of the via bar, a portion of the second surface of the memory die extending over the first surface of the logic die, such that the logic die and the memory die are vertically staggered, and the memory die electrically coupled to the logic die through the via bar. The via bar can be formed from glass, and include through-glass vias (TGVs) and embedded passives such as resistors, capacitors, and inductors. The semiconductor device can be formed as a single package or a package-on-package structure with the via bar and the memory die encapsulated in a package and the substrate and logic die in another package.

First claim

What is claimed is:

1. A device comprising:
a second surface of a logic die, a second surface of a first glass via bar, and a second surface of a second glass via bar coupled to a first surface of a substrate;
a second surface of a first memory die coupled to a first surface of the first glass via bar, a second surface of a second memory die coupled to a first surface of the second glass via bar, a portion of the second surface of the first memory die and a portion of the second surface of the second memory die extending over the first surface of the logic die, such that the logic die and the first memory die are vertically staggered and the logic die and the second memory die are vertically staggered; and
the first memory die electrically coupled to the logic die through the first glass via bar and the second memory die electrically coupled to the logic die through the second glass via bar, and the second memory die electrically coupled to the logic die through the second glass via bar, wherein one or more through-glass vias (TGVs) are formed within the first glass via bar and the second glass via bar.

2. The device of claim 1 , wherein the first memory die and the second memory die each comprises a dynamic random access memory (DRAM) die.

3. The device of claim 2 , wherein each DRAM die has wide input/output (I/O) interfaces.

4. The device of claim 3 , wherein the each DRAM die is one of a plurality of DRAM dies formed on a DRAM wafer, and wherein each of the plurality of DRAM dies comprises one or more attached glass via bars.

5. The device of claim 4 , wherein the one or more attached glass via bars are configured as space transformers to enable full wafer contractor probing of the DRAM wafer, at a coarse pitch, during testing of the DRAM wafer.

6. The device of claim 5 , wherein one or more known good DRAM dies of the plurality of the DRAM dies formed on the DRAM wafer are determined based on the coarse pitch probing.

7. The device of claim 4 , wherein each of the plurality of DRAM dies comprising the one or more attached glass via bars are configured for single package or package-on-package (PoP) structures.

8. The device of claim 1 , further comprising one or more additional memory dies.

9. The device of claim 8 , wherein the one or more additional memory dies are stacked on to a first surface of the first memory die and electrically connected to the first memory die through one or more through-silicon vias (TSVs).

10. The device of claim 8 , wherein the one or more additional memory dies are electrically coupled to the logic die through one or more additional glass via bars.

11. The device of claim 1 , further comprising a third memory die electrically coupled to the logic die through a third glass via bar, wherein the third glass via bar is attached to a second surface of the substrate.

12. The device of claim 1 , wherein the first memory die comprises a lead on a center of the second surface of the first memory die for formation of an electrical contact with the first surface of the first via bar.

13. The device of claim 1 , wherein passive components are embedded in the first glass via bar.

14. The device of claim 13 , wherein the passive components comprise one or more of resistors, inductors, and capacitors.

15. The device of claim 13 , wherein the passive components are configured to improve power delivery to the logic die.

16. The device of claim 1 encapsulated in a single package.

17. The device of claim 1 , wherein the logic die and the substrate are encapsulated in a first package and the first memory die and the first via bar are encapsulated in a second package, wherein the first package and the second package are attached in a package-on-package (PoP) structure.

18. A device comprising:
a substrate having a first surface and a second surface opposite the first surface;
a logic die having a first surface and a second surface opposite the first surface;
a glass via bar having a first surface and a second surface opposite the first surface, the glass via bar including one or more through-glass vias (TGVs) formed within the glass via bar to electrically connect the first surface of the glass via bar to the second surface of the glass via bar, wherein the second surface of the logic die and the second surface of the glass via bar are coupled to the first surface of the substrate; and
a dynamic random access memory (DRAM) die having a first surface and a second surface opposite the first surface, wherein the second surface of the DRAM die is coupled to the first surface of the glass via bar, and wherein the second surface of the DRAM die extends over the first surface of the logic die such that the logic die and the DRAM die are vertically staggered, the DRAM die and the logic die being electrically coupled through the glass via bar, the DRAM die being one of a plurality of DRAM dies formed on a DRAM wafer, and wherein each of the plurality of DRAM dies includes one or more attached glass via bars configured as space transformers to enable full wafer contractor probing of the DRAM wafer, at a coarse pitch, during testing of the DRAM wafer.

19. The device of claim 18 , wherein one or more known good DRAM dies of the plurality of the DRAM dies formed on the DRAM wafer are determined based on the coarse pitch probing.

20. The device of claim 18 , wherein the DRAM die has wide input/output (I/O) interfaces.

21. The device of claim 18 , further comprising:
a plurality of passive components embedded in the glass via bar.

22. A device comprising:
a substrate having a first surface and a second surface opposite the first surface;
a logic die having a first surface and a second surface opposite the first surface, wherein the logic die and the substrate are encapsulated in a first package;
a glass via bar having a first surface and a second surface opposite the first surface, the glass via bar including one or more through-glass vias (TGVs) formed within the glass via bar to electrically connect the first surface of the glass via bar to the second surface of the glass via bar, wherein the second surface of the logic die and the second surface of the glass via bar are coupled to the first surface of the substrate; and
a memory die having a first surface and a second surface opposite the first surface, wherein the second surface of the memory die is coupled to the first surface of the glass via bar, the second surface of the memory die extending over the first surface of the logic die such that the logic die and the memory die are vertically staggered, the memory die and the logic die being electrically coupled through the glass via bar, wherein the memory die and the glass via bar are encapsulated in a second package, the first package and the second package being attached in a package-on-package (PoP) structure.

23. The device of claim 22 , wherein the memory die includes a dynamic random access memory (DRAM) die, wherein the DRAM die is one of a plurality of DRAM dies formed on a DRAM wafer, each of the plurality of DRAM dies including one or more attached glass via bars configured as space transformers to enable full wafer contractor probing of the DRAM wafer, at a coarse pitch, during testing of the DRAM wafer.

24. The device of claim 23 , wherein one or more known good DRAM dies of the plurality of the DRAM dies formed on the DRAM wafer are determined based on the coarse pitch probing.

25. The device of c

Assignees

• Qualcomm Inc
• Qualcomm Mems Technologies Inc

Inventors

• Shenoy Ravindra Vaman
• Lai Kwan-Yu
• Lasiter Jon Bradley
• Stephanou Philip Jason
• Kidwell Jr Donald William
• Gousev Evgeni

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title