Multichip modules and methods of fabrication

Patent metadata

Field	Value
Publication number	US-9666559-B2
Application number	US-201514809036-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Sep 5, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

In a multi-chip module (MCM), a “super” chip ( 110 N) is attached to multiple “plain” chips ( 110 F; “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips ( 110 F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

First claim

The invention claimed is:

1. A manufacturing process comprising:
(1) obtaining a plurality of assemblies, wherein obtaining each assembly of said assemblies comprises performing a process comprising:
obtaining a plurality of first modules for the assembly, each first module being a single-chip or multi-chip module comprising circuitry;
placing first molding compound in physical contact with each first module, and curing the first molding compound, to form a first structure in which the first modules are held together by at least the first molding compound, wherein the circuitry of each of at least two of the first modules has one or more first contact pads and one or more second contact pads on a bottom side of the first structure;
forming one or more layers on the bottom side of the first structure, the one or more layers providing bottom-side circuitry connected to one or more of the second contact pads on the bottom side of the first structure;
forming one or more first through-holes through the first molding compound, each first through-hole passing between top and bottom sides of the first molding compound; and
forming one or more first conductive vias in the one or more first through-holes, each first conductive via reaching and physically contacting the bottom-side circuitry, each first conductive via being accessible from the top side of the first molding compound;
obtaining one or more second modules each of which comprises circuitry with one or more first contact pads, each second module being a single-chip or multi-chip module; and
attaching each second module below the bottom side of the first structure to form a second structure in which each second module and the first modules are interconnected through the first contact pads of the first and second modules;
forming second molding compound on a bottom side of the second structure;
forming one or more second through-holes through the second molding compound, each second through-hole passing between top and bottom sides of the second molding compound; and
forming one or more second conductive vias in the one or more second through-holes, each second conductive via reaching and physically contacting the bottom-side circuitry, each second conductive via being accessible from the bottom side of the second molding compound;
(2) forming a stack of said assemblies, wherein for each two adjacent assemblies in the stack, at least one second conductive via of one of the two adjacent assemblies is attached to at least one first conductive via of the other one of the two adjacent assemblies.

2. A manufacturing process comprising:
obtaining a plurality of first modules each of which is a single-chip or multi-chip module comprising circuitry;
placing first molding compound in physical contact with each first module, and curing the first molding compound, to form a first structure in which the first modules are held together by at least the first molding compound, wherein the circuitry of each of at least two of the first modules has one or more first contact pads and one or more second contact pads on a bottom side of the first structure;
forming one or more layers on the bottom side of the first structure, the one or more layers providing bottom-side circuitry connected to one or more of the second contact pads on the bottom side of the first structure;
forming one or more first through-holes through the first molding compound, each first through-hole passing between top and bottom sides of the first molding compound; and
forming one or more first conductive vias in the one or more first through-holes, each first conductive via reaching and physically contacting the bottom-side circuitry, each first conductive via being accessible from the top side of the first molding compound.

3. The process of claim 2 further comprising:
obtaining one or more second modules each of which comprises circuitry with one or more first contact pads, each second module being a single-chip or multi-chip module; and
attaching each second module below the bottom side of the first structure to form an assembly in which each second module and the first modules are interconnected through the first contact pads of the first and second modules.

4. The process of claim 3 further comprising:
forming second molding compound on a bottom side of the assembly;
forming one or more second through-holes through the second molding compound, each second through-hole passing between top and bottom sides of the second molding compound; and
forming one or more second conductive vias in the one or more second through-holes, each second conductive via reaching and physically contacting the bottom-side circuitry, each second conductive via being accessible from the bottom side of the second molding compound.

5. A manufacturing process comprising:
obtaining a plurality of assemblies, wherein obtaining each of the assemblies comprises performing a process according to claim 4 ; and
forming a stack of said assemblies, wherein for each two adjacent assemblies in the stack, at least one second conductive via of one of the two adjacent assemblies is attached to at least one first conductive via of the other one of the two adjacent assemblies.

6. A manufacturing process comprising:
obtaining a plurality of assemblies, wherein obtaining each of the assemblies comprises performing a process according to claim 2 ; and
forming a stack of said assemblies, wherein for each two adjacent assemblies in the stack, at least one second conductive via of one of the two adjacent assemblies is attached to at least one first conductive via of the other one of the two adjacent assemblies.

7. The process of claim 1 wherein in each said assembly, in said attaching each second module, at least one second module underlies at least two corresponding first modules and has at least two first contact pads attached to respective two first contact pads of respective different ones of the corresponding first modules.

8. The process of claim 1 wherein in each said assembly, in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first modules with each attachment being by solder or diffusion bonding.

9. The process of claim 1 wherein in each said assembly, in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first modules with each attachment being by conductive or anisotropic adhesive.

10. The process of claim 9 wherein the adhesive is a polymeric adhesive.

11. The process of claim 10 wherein the adhesive is an organic polymeric adhesive.

12. The process of claim 1 wherein each said module is a chip.

13. The process of claim 3 wherein in said attaching each second module, at least one second module underlies at least two corresponding first modules and has at least two first contact pads attached to respective two first contact pads of respective different ones of the corresponding first modules.

14. The process of claim 3 wherein in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first modules with each attachment being by solder or diffusion bonding.

15. The process of claim 3 wherein in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first mo

Assignees

• Invensas Corp

Inventors

• Wang Liang
• Katkar Rajesh
• Shen Hong

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/752

  between stacked chips · CPC title