Test key design to enable X-ray scatterometry measurement

Patent metadata

Field	Value
Publication number	US-10499876-B2
Application number	US-201715725857-A
Country	US
Kind code	B2
Filing date	Oct 5, 2017
Priority date	Jul 31, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A method includes forming a test key. The formation of the test key includes forming a first plurality of semiconductor strips, and cutting the first plurality of semiconductor strips into an array of a second plurality semiconductor strips, with each row of the array being formed from one strip in the first plurality of semiconductor strips, forming isolation regions in recesses between the second plurality of semiconductor strips, and recessing the isolation regions. The top portions of the second plurality of semiconductor strips protrude higher than the isolation regions form semiconductor fins, which form a fin array. An X-ray beam is projected on the test key. A diffraction pattern is obtained from scattered X-ray beam scattered from the test key.

First claim

What is claimed is:

1. A method comprising:
forming a test key comprising:
forming a first plurality of semiconductor strips;
cutting the first plurality of semiconductor strips into an array of a second plurality semiconductor strips, wherein each row of the array is formed from one strip in the first plurality of semiconductor strips;
forming isolation regions in recesses between the second plurality of semiconductor strips; and
recessing the isolation regions, wherein top portions of the second plurality of semiconductor strips protrude higher than the isolation regions to form semiconductor fins, and the semiconductor fins form a fin array;

projecting an X-ray beam on the test key; and
obtaining a diffraction pattern from scattered X-ray beam scattered from the test key.

2. The method of claim 1 , wherein the first and the second plurality of semiconductor strips are formed using a manufacturing technology, and spacings of the second plurality semiconductor strips in a same row is a minimum spacing of the manufacturing technology.

3. The method of claim 1 , wherein the first plurality of semiconductor strips has a uniform pitch.

4. The method of claim 1 , wherein the array has a first uniform pitch between rows of the fin array, and a second uniform pitch between columns of the fin array.

5. The method of claim 1 further comprising determining a parameter from the diffraction pattern, with the parameter selected from a pitch of the semiconductor fins, a width of the semiconductor fins, and a height of the semiconductor fins.

6. The method of claim 1 , wherein the forming the test key further comprises:
forming a plurality of gate structures covering first portions of the semiconductor fins; and
etching second portions of the semiconductor fins extending beyond the plurality of gate structures to form recesses.

7. The method of claim 1 , wherein the forming the test key further comprises:
forming an inter-layer dielectric over the semiconductor fins;
forming an array of recesses in the inter-layer dielectric to expose portions of the semiconductor fins; and
forming a high-k dielectric layer extending into the array of recesses.

8. The method of claim 7 , wherein the forming the test key further comprises forming a metal layer over the high-k dielectric layer.

9. The method of claim 1 , wherein the test key is a composite test key comprising:
a plurality of sub-test keys, with each of the sub-test keys comprising a plurality of semiconductor fins forming a sub-array; and
random patterns of semiconductor fins filling spaces between the sub-test keys.

10. The method of claim 1 , wherein the test key has a non-rectangular contour.

11. A method comprising:
forming an array of semiconductor fins, wherein the semiconductor fins have a same length, and the array has a plurality of rows and a plurality of columns;
forming additional features over the semiconductor fins, wherein the additional features comprise at least a plurality of columns, with each column over a column of the semiconductor fins;
obtaining an X-ray diffraction pattern from the array of semiconductor fins and the additional features; and
determining dimensions of the additional features from the X-ray diffraction pattern.

12. The method of claim 11 , wherein the forming the additional features comprises forming gate structures, each extending throughout an entire column of the semiconductor fins.

13. The method of claim 12 , wherein the forming the additional features further comprises:
etching portions of the semiconductor fins not covered by the gate structures to form recesses extending into isolation regions, wherein the determining the dimensions comprises determining depths of the recesses.

14. The method of claim 11 , wherein the forming the additional features comprises:
forming an inter-layer dielectric over the semiconductor fins;
etching the inter-layer dielectric to form an additional array of recesses extending into the inter-layer dielectric;
forming a high-k dielectric layer extending into the additional array of recesses; and
forming a metal layer over the high-k dielectric layer, wherein the determining dimensions of the additional features comprises determining thicknesses of the high-k dielectric layer and the metal layer.

15. The method of claim 11 , wherein the obtaining the X-ray diffraction pattern comprises projecting an X-ray beam onto the array and the additional features, and receiving the X-ray diffraction pattern from scattered X-ray beam scattered from the array and the additional features.

16. The method of claim 11 , further comprising forming a plurality of semiconductor fins around the array, wherein the plurality of semiconductor fins is allocated in a random pattern.

17. The method of claim 11 , wherein the array of semiconductor fins has a size greater than about 50 μm×50 μm.

18. A method comprising:
forming a test key comprising:
forming an array of semiconductor fins, wherein the semiconductor fins have a same length, and the array has a plurality of rows and a plurality of columns;
forming a plurality of gate structures overlying the semiconductor fins, wherein the plurality of gate structures is distributed substantially uniformly throughout the array, and the plurality of gate structures has a lengthwise direction perpendicular to a lengthwise direction of the semiconductor fins; and
etching portions of the semiconductor fins not covered by the plurality of gate structures to form recesses extending into isolation regions;

obtaining an X-ray diffraction pattern from the test key; and
determining dimensions of the semiconductor fins and the plurality of gate structures from the X-ray diffraction pattern.

19. The method of claim 18 , wherein each of the plurality of gate structures extends from a first end of the array to an opposite second end of the array.

20. The method of claim 18 , wherein the determining the dimensions comprises determining depths of the recesses and at least one of pitches, widths, and heights of the semiconductor fins.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ferng Shyh-Shin
• Huang Chung-Li
• Lin Yi-Hung
• Wang Chungwei

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27 Primary

  Structural arrangements therefor · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title