Semiconductor constructions which include metal-containing gate portions and semiconductor-containing gate portions

Patent metadata

Field	Value
Publication number	US-10497707-B2
Application number	US-201715439282-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Jan 10, 2013
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

First claim

We claim:

1. A semiconductor construction, comprising:
a channel region;
gate dielectric directly against the channel region; the gate dielectric comprising one or more oxides;
a semiconductor-containing gate portion along a first segment of the channel region and spaced from said first segment by at least the gate dielectric; the semiconductor-containing gate portion consisting of conductively-doped semiconductor material;
a metal-containing gate portion along a second segment of the channel region and spaced from said second segment by at least the gate dielectric; the second segment being adjacent the first segment; the metal-containing gate portion being directly against the semiconductor-containing gate portion; and
the semiconductor-containing gate portion, metal-containing gate portion, dielectric material and channel region comprising a transistor.

2. The semiconductor construction of claim 1 wherein the metal-containing gate portion and the semiconductor-containing gate portion are both directly against the gate dielectric.

3. The semiconductor construction of claim 2 wherein the metal-containing gate portion is a first metal-containing gate portion, and further comprising a second metal-containing gate portion directly against the gate dielectric and spaced from the first metal-containing gate portion by the semiconductor-containing gate portion.

4. The semiconductor construction of claim 2 wherein the semiconductor-containing gate portion is a first semiconductor-containing gate portion, and further comprising a second semiconductor-containing gate portion directly against the gate dielectric and spaced from the first semiconductor-containing gate portion by the metal-containing gate portion.

5. The semiconductor construction of claim 1 wherein the metal-containing gate portion and the semiconductor-containing gate portion are both directly against an electrically conductive material, which in turn is directly against the gate dielectric.

6. The semiconductor construction of claim 5 wherein the metal-containing gate portion is a first metal-containing gate portion, and further comprising a second metal-containing gate portion directly against the electrically conductive material and spaced from the first metal-containing gate portion by the semiconductor-containing gate portion.

7. The semiconductor construction of claim 5 wherein the semiconductor-containing gate portion is a first semiconductor-containing gate portion, and further comprising a second semiconductor-containing gate portion directly against the electrically conductive material and spaced from the first semiconductor-containing gate portion by the metal-containing gate portion.

8. The semiconductor construction of claim 1 wherein the channel region is over an upper surface of a base and extends substantially vertically relative to such upper surface.

9. A semiconductor construction, comprising:
a channel region over an upper surface of a silicon-containing base and extending substantially vertically relative to such upper surface;
gate dielectric directly against the channel region;
a semiconductor-containing gate portion along a first segment of the channel region and spaced from said first segment by at least the gate dielectric; the semiconductor-containing gate portion consisting of conductively-doped semiconductor material;
a metal-containing gate portion along a second segment of the channel region and spaced from said second segment by at least the gate dielectric; the second segment being adjacent the first segment; the metal-containing gate portion being directly against the semiconductor-containing gate portion;
the semiconductor-containing gate portion, metal-containing gate portion, dielectric material and channel region comprising a transistor; and
a NAND string electrically coupled with the transistor.

10. The semiconductor construction of claim 9 wherein:
the channel region is configured as a pillar laterally surrounded by the gate dielectric; and
the metal-containing gate portion and the semiconductor-containing gate portion entirely laterally surround said pillar; with the metal-containing gate portion being over the semiconductor-containing gate portion.

Assignees

• Micron Technology Inc

Inventors

• Thimmegowda Deepak
• Bicksler Andrew R
• Awusie Roland

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D64/0132

  the conductor being a metallic silicide · CPC title

• H01L29/78

  Electricity · mapped topic

• H01L29/7828

  Electricity · mapped topic